Search Results - "FPGA clusters"

Accelerating many-core, heterogeneous, and distributed architectures with hardware runtimes and programming models

Authors: De Haro Ruiz, Juan Miguel

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Álvarez Martínez, Carlos, Jiménez González, Daniel

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: High Performance Computing (HPC), Field-Programmable Gate Array (PFGA), task scheduling, task-based programming models, computer architecture, CPU, MPI, High-Level Synthesis (HLS), energy efficiency, programmability, many-core architectures, FPGA clusters, hardware runtimes, hardware acceleration, ASIC, Implicit Message Passing (IMP), Àrees temàtiques de la UPC::Informàtica, 004 - Informàtica

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/695347
https://dx.doi.org/10.5821/dissertation-2117-442722

Enabling high-level parallel programming on multi-FPGA clusters

Authors: Haro Ruiz, Juan Miguel de Álvarez Martínez, Carlos Jiménez González, Daniel et al.

Source: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)

Subject Terms: Matrius de portes programables per l'usuari, FPGA clusters, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, High-level parallel programming, Field programmable gate arrays, Parallel programming (Computer science), MPI, High-level synthesis (HLS), High performance computing, Programació en paral·lel (Informàtica), Càlcul intensiu (Informàtica), Task-based programming, Distributed memory

File Description: application/pdf

Access URL: https://hdl.handle.net/2117/411960
https://doi.org/10.1145/3665283.3665292

Abstracting OpenCL for Multi-Application Workloads on CPU-FPGA Clusters

Authors: Holland, Graham

Subject Terms: Field-programmable gate arrays, Runtime task scheduling, OpenCL, Hardware acceleration, FPGA clusters

Relation: https://summit.sfu.ca/_flysystem/fedora/sfu_migrate/19824/etd20700.pdf

Availability: https://summit.sfu.ca/_flysystem/fedora/sfu_migrate/19824/etd20700.pdf

Enabling high-level parallel programming on multi-FPGA clusters

Authors: Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Barcelona Supercomputing Center et al.

Index Terms: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Field programmable gate arrays, High performance computing, Parallel programming (Computer science), Task-based programming, MPI, FPGA clusters, Distributed memory, High-level parallel programming, High-level synthesis (HLS), Matrius de portes programables per l'usuari, Càlcul intensiu (Informàtica), Programació en paral·lel (Informàtica), Conference report

URL: https://hdl.handle.net/2117/411960
https://dl.acm.org/doi/10.1145/3665283.3665292
https://dl.acm.org/doi/10.1145/3665283.3665292
info:eu-repo/grantAgreement/EC/H2020/946002/EU/The MareNostrum Experimental Exascale Platform/MEEP
info:eu-repo/grantAgreement/EC/H2020/956831/EU/Towards EXtreme scale Technologies and Accelerators for euROhpc hw%2FSw Supercomputing Applications for exascale/TEXTAROSSA
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PCI2021-121964/ES/TOWARDS EXTREME SCALE TECHNOLOGIES AND ACCELERATORS FOR EUROHPC HW%2FSW SUPERCOMPUTING APPLICATIONS FOR EXASCALE
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/PDC2022-133323-I00/ES/PROCESADOR FUERA DE ORDEN MULTINUCLEO CONSCIENTE DE LA APLICACION BASADO EN INSTRUCCIONES ABIERTAS RISC-V
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C21/ES/BSC - COMPUTACION DE ALTAS PRESTACIONES VIII

CHEF: A Framework for Deploying Heterogeneous Models on Clusters with Heterogeneous FPGAs.

Authors: Tang Y Song Y Elango N et al.

Source: IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society [IEEE Trans Comput Aided Des Integr Circuits Syst] 2024 Nov; Vol. 43 (11), pp. 3937-3948. Date of Electronic Publication: 2024 Nov 06.

Publication Type: Journal Article

Journal Info: Publisher: Institute of Electrical and Electronics Engineers Country of Publication: United States NLM ID: 101210570 Publication Model: Print-Electronic Cited Medium: Internet ISSN: 1937-4151 (Electronic) Linking ISSN: 02780070 NLM ISO Abbreviation: IEEE Trans Comput Aided Des Integr Circuits Syst Subsets: PubMed not MEDLINE