Search Results - "FPGA Implementation"

Contributions to RFI detection, mitigation, and excision for GNSS receivers and spaceborne microwave radiometers

Authors: Pérez Portero, Adrián

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions

Thesis Advisors: Camps Carmona, Adriano José, Hyuk, Park

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: Radio Frequency Interference (RFI), GNSS Reflectometry (GNSS-R), Microwave Radiometry, Signal Processing, Remote Sensing, Polarimetric Detection, FPGA Implementation, Space-Qualified Systems, SMAP-R Mission, Bistatic Radar, Interference Mitigation, Earth Observation, Scattering Models, Real-Time Processing, Software-Defined Radio, Àrees temàtiques de la UPC::Enginyeria de la telecomunicació, 621.3 - Enginyeria elèctrica. Electrotècnia. Telecomunicacions

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/694489
https://dx.doi.org/10.5821/dissertation-2117-430037

Energy-efficient fpga-based hardware-software co-design of the Skein algorithm for secure edge computing in smart grids

Authors: Salimi Shahraki, Atefeh Abbasi, Mahdi

Source: Journal of Power Technologies. 105(3):270-285

Subject Terms: smart grids, energy-efficient cryptography, FPGA implementation, hardware-software co-design, secure edge computing

File Description: electronic

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-246433
https://papers.itc.pw.edu.pl/index.php/JPT/article/view/1937

Highly scalable hardware architecture for real-time execution of spiking neural networks applied to neural cognitive applications

Authors: Vallejo Mancero, Bernardo Javier

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica

Thesis Advisors: Madrenas Boadas, Jordi, Zapata Rodríguez, Mireya Patricia

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: Spiking Neural Networks (SNN), Neuromorphic Computing, HEENS Architecture, Real-time Processing, FPGA Implementation, Synaptic Plasticity, Spiking neural models, Real-time sensor processing, Redes Neuronales de Impulsos (SNN), Computación Neuromórfica, Procesamiento en Tiempo Real, Implementación en FPGA, Plasticidad Sináptica, Modelos Neuronales de Impulsos, Procesamiento de Sensores en Tiempo Real, Xarxes Neuronals de POlsos (SNN), Computació Neuromòrfica, Arquitectura HEENS, Processament en Temps Real, Implementació en FPGA, Plasticitat Sinàptica, Models Neuronals de Polsos, Processament de Sensors en Temps Real, Àrees temàtiques de la UPC::Enginyeria electrònica, Àrees temàtiques de la UPC::Informàtica, 621.3 - Enginyeria elèctrica. Electrotècnia. Telecomunicacions, 004 - Informàtica

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/694228
https://dx.doi.org/10.5821/dissertation-2117-427834

A novel conservative vortex‑like chaotic system with tunable parameters and its application in audio encryption

Authors: Anna Guo Chengbin Xu Chunlei Fan

Source: Journal of King Saud University: Computer and Information Sciences, Vol 37, Iss 9, Pp 1-26 (2025)

Subject Terms: Conservative chaotic system, Vortex-like, Circuit implementation, FPGA implementation, Audio encryption, Security analysis, Electronic computers. Computer science, QA75.5-76.95

File Description: electronic resource

Relation: https://doaj.org/toc/1319-1578; https://doaj.org/toc/2213-1248

Access URL: https://doaj.org/article/76f030b8ac4444a89c67eeb2eb54222f

An optimized novel lightweight block cipher for image encryption

Authors: R. Mohanapriya Kumar V. Nithish

Source: Scientific Reports, Vol 15, Iss 1, Pp 1-16 (2025)

Subject Terms: Lightweight cryptography, ARX cipher, Cryptanalysis, Image encryption, Key schedule, FPGA implementation, Medicine, Science

File Description: electronic resource

Relation: https://doaj.org/toc/2045-2322

Access URL: https://doaj.org/article/df64e9ac3c4d4b049f81ba3c22d84002

Exploring Dynamics and Hardware Implementation of an Enhanced 5D Hyperchaotic Memristive System Inspired by Sprott-C System

Authors: Abdulmajeed Abdullah Mohammed Mokbel Fei Yu Yumba Musoya Gracia et al.

Source: Complex System Modeling and Simulation, Vol 5, Iss 1, Pp 34-45 (2025)

Subject Terms: TA168, numerical simulation, Electronic computers. Computer science, sprott-c system, field-programmable gate array (fpga) implementation, QA75.5-76.95, memristor, hyperchaotic system, Systems engineering

Access URL: https://doaj.org/article/5dedac800e764d8bb0362f90800c70ad

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Authors: Batista, Gracieth Cavalcanti Öberg, Johnny Saotome, Osamu et al.

Source: Journal of Electronic Science and Technology. 22(2)

Subject Terms: Dynamic partial reconfiguration (DPR), Field programmable gate array (FPGA) implementation, Image edge detection, Support vector regression (SVR), Unmanned aerial vehicle (UAV) pose estimation

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-346160
https://doi.org/10.1016/j.jnlest.2024.100248

A new fast high dimensional and memristive hyperchaotic multiple image encryption method and its FPGA implementation

Authors: Wassim Alexan Youstina Megalli

Source: Discover Electronics, Vol 2, Iss 1, Pp 1-33 (2025)

Subject Terms: Chaos-based image encryption, FPGA implementation, High-dimensional chaotic systems, Memristive neural networks, Multiple image encryption, Real-time cryptography, Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Mathematics, QA1-939

File Description: electronic resource

Relation: https://doaj.org/toc/2948-1600

Access URL: https://doaj.org/article/7c2dc89ff11f4e588ffe48ea56c23cfc

An area-efficient DSP-free modular exponentiation architecture for resource-constrained FPGAs

Authors: W. A. Susantha Wijesinghe

Source: Journal of King Saud University: Engineering Sciences, Vol 37, Iss 6, Pp 1-13 (2025)

Subject Terms: Modular arithmetic, FPGA implementation, Modular exponentiation, Cryptographic hardware, Resource-constrained systems, Engineering (General). Civil engineering (General), TA1-2040

File Description: electronic resource

Relation: https://doaj.org/toc/1018-3639; https://doaj.org/toc/2213-1558

Access URL: https://doaj.org/article/68cb37599a4a4b20bcee4d9f1b0fa7f8

FPGA‐Based Design of Ultra‐Efficient Approximate Adders for High‐Fidelity Image Processing: A Logic‐Optimized Approach

Authors: Ramakrishna Reddy Eamani N. Vinodhkumar Ambe Harrison et al.

Source: Engineering Reports, Vol 7, Iss 7, Pp n/a-n/a (2025)

Subject Terms: FPGA implementation, low‐power logic, Electronic computers. Computer science, PSNR, QA75.5-76.95, TA1-2040, Engineering (General). Civil engineering (General), approximate computing, full adder design, image processing

Access URL: https://doaj.org/article/54fcce821391464cad11872294a9f4fe

Custom TTA Operations for Accelerating the Ascon Encryption Algorithm

Authors: Latif Akçay

Source: Volume: 7, Issue: 2123-132
Bayburt Üniversitesi Fen Bilimleri Dergisi

Subject Terms: Digital Processor Architectures, Hafif kriptografi, Komut seti genişletme, Uygulamaya özgü işlemci tasarımı, Özel işlemci tasarımı, FPGA gerçeklemesi, Dijital İşlemci Mimarileri, Gömülü Sistemler, Sayısal Tasarım, Embedded Systems, Lightweight cryptography, Instruction set extension, Custom processor design, Application-specific processor design, FPGA implementation, Numerical Design

File Description: application/pdf

Access URL: https://dergipark.org.tr/tr/pub/bufbd/issue/89325/1582809

Next-generation ECC processor on FPGA: Leveraging Koblitz curves for enhanced performance

Authors: Tung Nguyen Khai Nguyen Vy Nguyen et al.

Source: Ain Shams Engineering Journal, Vol 16, Iss 9, Pp 103495- (2025)

Subject Terms: Cryptography, ECPM, FPGA implementation, Hardware implementation, Brent-Kung, Montgomery ladder, Engineering (General). Civil engineering (General), TA1-2040

File Description: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2090447925002369; https://doaj.org/toc/2090-4479

Access URL: https://doaj.org/article/9fa87188c6be4c7393c2f965120a61ce

FPGA-Implementation of Lossless Integer Tchebichef Transform With Application for Tampering Detection in ROI Medical Images

Authors: Achraf Daoui Mohamed Yamni Chakir El-Kasri et al.

Source: IEEE Access, Vol 13, Pp 164026-164049 (2025)

Subject Terms: Lossless integer-to-integer transforms, lossless Tchebichef transform, FPGA implementation, embedded systems, ROI-tampering detection, medical imaging, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

File Description: electronic resource

Relation: https://ieeexplore.ieee.org/document/11168163/; https://doaj.org/toc/2169-3536

Access URL: https://doaj.org/article/2eb19e0feb254a3ab903985432d44b5c

A Comprehensive Survey on Delaunay Triangulation: Applications, Algorithms, and Implementations Over CPUs, GPUs, and FPGAs

Authors: Yahia S. Elshakhs Kyriakos M. Deliparaschos Themistoklis Charalambous et al.

Contributors: Yahia S. Elshakhs Kyriakos M. Deliparaschos Themistoklis Charalambous et al.

Source: IEEE Access, Vol 12, Pp 12562-12585 (2024)

Subject Terms: CPU implementation of Delaunay triangulation, GPU implementation of Delaunay triangulation, CPU implementation of Delaunay triangulation, Applications of Delaunay triangulation, Algorithmic approaches to Delaunay triangulation, GPU, applications of Delaunay triangulation, Delaunay triangulation, Electrical Engineering - Electronic Engineering - Information Engineering, GPU implementation of Delaunay triangulation, 7. Clean energy, FPGA implementation of Delaunay triangulation, TK1-9971, Engineering and Technology, algorithmic approaches to Delaunay triangulation, Electrical engineering. Electronics. Nuclear engineering, Voronoi diagram, CPU, FPGA

File Description: pdf; application/pdf

Access URL: https://doaj.org/article/df28eb2b0eb9498092a26e6d9b3f4f25
https://api.elsevier.com/content/abstract/scopus_id/85182928321
https://hdl.handle.net/20.500.14279/31370
https://aaltodoc.aalto.fi/handle/123456789/127181

A Hardware-Accelerated Approach to Chaotic Image Encryption: LTB Map and FPGA Implementation

Authors: Mohamed Yamni Achraf Daoui Paweł Pławiak et al.

Source: IEEE Access, Vol 12, Pp 103921-103940 (2024)

Subject Terms: FPGA implementation, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, LTB map, Electrical engineering. Electronics. Nuclear engineering, 02 engineering and technology, high-speed image encryption, 01 natural sciences, chaotic maps, TK1-9971

Access URL: https://doaj.org/article/42f09d3a2fda4751acc9e8123ba90665

Implementation and Evaluation of Two Independent Ising Machines on Same FPGA Board by Reducing Number of Interactions Inside Ising Machine

Authors: Shinjiro Kitahara Taichi Megumi Akari Endo et al.

Source: IEEE Access, Vol 12, Pp 145530-145539 (2024)

Subject Terms: Ising machine, FPGA implementation, interaction reduction, simulated annealing, Electrical engineering. Electronics. Nuclear engineering, annealing processor, Annealing, TK1-9971

Access URL: https://doaj.org/article/7488b85390b34cca80d4427100d34aea

A Compact and Low Latency SPM Architecture for ECC Cryptosystems

Authors: Khalid Javeed Fadi N. Sibai Ali El-Moursy

Source: IEEE Access, Vol 12, Pp 147552-147563 (2024)

Subject Terms: FPGA implementation, Scalar point multiplication, arithmetic circuits for finite fields, elliptic curve cryptography (ECC), Electrical engineering. Electronics. Nuclear engineering, Montgomery ladder, TK1-9971

Access URL: https://doaj.org/article/4ef2780c3abb4f8080a5a397044e12b8

Fuzzy Logic Control Implementation for Grid-Connected Multilevel Inverter Using FPGA-Based CORDIC-PLL Synchronization

Authors: Ali Ahmad Thenon Alnaqeeb Taha Ahmed Hussein

Source: NTU Journal of Engineering and Technology, Vol 4, Iss 2 (2025)

Subject Terms: grid-connected inverter, fuzzy logic control, cordic-pll, multilevel inverter, fpga implementation, synchronization, active current control, reactive current control, Engineering (General). Civil engineering (General), TA1-2040

File Description: electronic resource

Relation: https://journals.ntu.edu.iq/index.php/NTU-JET/article/view/1199; https://doaj.org/toc/2788-9971; https://doaj.org/toc/2788-998X

Access URL: https://doaj.org/article/174077b4e2554247a276d41687d260df

Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications

Authors: Venkata Sudhakar Chowdam Suresh Babu Potladurty Prasad Reddy karipireddy

Source: Memories - Materials, Devices, Circuits and Systems, Vol 9, Iss , Pp 100123- (2025)

Subject Terms: Approximate computing, Approximate adders, Clock-gating multiplier, Verilog HDL, FPGA implementation, Power efficiency, Electric apparatus and materials. Electric circuits. Electric networks, TK452-454.4, Computer engineering. Computer hardware, TK7885-7895

File Description: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2773064625000039; https://doaj.org/toc/2773-0646

Access URL: https://doaj.org/article/554e0fe67b504f35849d8291a01a184c

Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural Network

Authors: Luhulima, Edgar Abernot, Madeleine Corradi, Federico et al.

Source: 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). :1-6

Subject Terms: 0301 basic medicine, Artificial intelligence, 0303 health sciences, 03 medical and health sciences, FPGA implementation, pattern recognition, Hebbian learning, oscillatory neural network, auto-associative memory

Access URL: https://research.tue.nl/en/publications/b307ec72-72de-4ed8-bd06-280f966d11af
https://doi.org/10.1109/ISLPED58423.2023.10244501