Search Results - "FPGA(Field Programmable Gate Array) implementation"

FPGA-Implementation of Electronic Voting Machine (EVM).

Authors: Kumar, Abhishek

Source: Majlesi Journal of Telecommunication Devices; Mar2025, Vol. 14 Issue 1, p31-38, 8p

Subject Terms: VOTING machines, GATE array circuits, DATA integrity, VOTING, DIGITAL technology

FPGA Implementation of a high-speed frame buffer for Smartglasses

Subject Terms: �������������� ������������������, ������������ ������������, Smartglasses, Digital Circuits, FPGA(Field Programmable Gate Array) Implementation, ������������������ ���� FPGA(Field Programmable Gate Array)

Hybrid statistical and recurrent neural network architecture implementation in FPGA device used for severe acute respiratory syndrome coronavirus detector.

Authors: Senthilkumar, V.M. Thenmozhi, S. Kumudavalli, M.V. et al.

Source: Journal of Intelligent & Fuzzy Systems; 2023, Vol. 44 Issue 6, p8803-8816, 14p

Subject Terms: SARS disease, CORONAVIRUSES, FIELD programmable gate arrays, BLIND source separation, INDEPENDENT component analysis, RECURRENT neural networks

BP神经网络FPGA实现结构的优化设计. (Chinese)

Alternate Title: Optimal Design of FPGA Implementation Structure for BP Neural Network. (English)

Authors: 谭会生 徐界铭 张驾祥

Source: Journal of Computer Engineering & Applications; Nov2022, Vol. 58 Issue 21, p264-271, 8p

Subject Terms: FIELD programmable gate arrays, QUADRATIC equations, COMPUTATIONAL complexity, RANDOM access memory, ORDER picking systems, HARBORS

High anti-interference and FPGA-oriented method for real-time ship detection based on structured LBP features.

Authors: Miao, Rui Jiang, Hongxu Tian, Fangzheng et al.

Source: Journal of Supercomputing; Jul2022, Vol. 78 Issue 11, p13780-13813, 34p

Subject Terms: GATE array circuits, REMOTE sensing, PROCESS capability, SHIPS, MILITARY research

Reconfigurable FPGA-Based Solvers For Sparse Satellite Control

Authors: Hamadouche, Anis Wu, Yun Sellathurai, Mathini et al.

Index Terms: Electrical Engineering and Systems Science - Signal Processing, Electrical Engineering and Systems Science - Systems and Control, text

URL: http://arxiv.org/abs/2406.00402

FPGA-realization of the kinematics IP for SCARA robot.

Authors: Chen, Wen-Chuan Chen, Chin-Sheng Lee, Feng-Chi et al.

Source: Microsystem Technologies; Apr2021, Vol. 27 Issue 4, p1075-1090, 16p

Subject Terms: FIELD programmable gate arrays, KINEMATICS, ROBOT motion, FINITE state machines, ROBOT kinematics

FPGA Implementation of SC-FDE Timing Synchronization Algorithm.

Authors: Suyuan Ji Chao Chen Yu Zhang

Source: Journal of Information Processing Systems; Aug2019, Vol. 15 Issue 4, p890-903, 14p

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Index Terms: NTT, CBD, Parse, VHDL, FPGA, Kyber

URL: http://hdl.handle.net/11012/208656
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
Proceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Index Terms: NTT, CBD, Parse, VHDL, FPGA, Kyber

URL: http://hdl.handle.net/11012/208656
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
Proceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Index Terms: NTT, CBD, Parse, VHDL, FPGA, Kyber

URL: http://hdl.handle.net/11012/208656
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
Proceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Authors: Jedlicka, Petr Hajny, Jan

Index Terms: NTT, CBD, Parse, VHDL, FPGA, Kyber

URL: http://hdl.handle.net/11012/208656
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
Proceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni

Empowering quadrature mirror filter bank architectures: dynamic-grey wolf optimization approach for elevated filter orders.

Authors: Daulat, Himani Chauhan, Krishna Varma, Tarun

Source: Engineering Optimization; Jun2025, Vol. 57 Issue 6, p1575-1603, 29p

Subject Terms: FILTER banks, REAL-time control, TRANSFER functions, COMPUTATIONAL complexity, ALGORITHMS

Area efficient reconfigurable architecture for current control loop of a servo controller.

Authors: Shreyas, S. G. Vachhani, Leena

Source: 2012 IEEE 7th International Conference on Industrial & Information Systems (ICIIS); 1/ 1/2012, p1-6, 6p

On the FPGA implementation of tracking algorithms.

Authors: Belaabed, A. Benbouchama, Ch.

Source: 2012 20th Mediterranean Conference on Control & Automation (MED); 1/ 1/2012, p1456-1461, 6p

Real-Time Multi-Object Tracking using YOLOv8 and SORT on a SoC FPGA

Authors: Danilowicz, Michal Kryjak, Tomasz

Subject Terms: FOS: Computer and information sciences, Computer Vision and Pattern Recognition (cs.CV), Computer Science - Computer Vision and Pattern Recognition

Access URL: http://arxiv.org/abs/2503.13023

A State-Feedback Control Strategy Based on Grey Fast Finite-Time Sliding Mode Control for an H-Bridge Inverter with LC Filter Output.

Authors: Chang, En-Chih Wu, Rong-Ching Chang, Heidi H. et al.

Source: Electronics (2079-9292); Jun2024, Vol. 13 Issue 11, p2118, 23p

Subject Terms: SLIDING mode control, AC DC transformers, UNINTERRUPTIBLE power supply, RENEWABLE energy sources, PSYCHOLOGICAL feedback, TRANSISTOR circuits, ALTERNATING current electric motors, REACTION time

A real-time FPGA implementation of spectrum sensing applying for DVB-T primary signal.

Authors: Nguyen, Tu T. Dang, Khoa L. Nguyen, Ha V. et al.

Source: 2013 International Conference on Advanced Technologies for Communications (ATC 2013); 2013, p164-169, 6p

FPGA implementation of neural network for linearization of thermistor characteristics.

Authors: Sonowal, Durlav Bhuyan, Manabendra

Source: 2012 International Conference on Devices, Circuits & Systems (ICDCS); 2012, p422-426, 5p

Toward a Solution of the Reverse Engineering Problem Using FPGAs.

Authors: Hutchison, David Kanade, Takeo Kittler, Josef et al.

Source: Euro-Par 2006: Parallel Processing. 2007, p304-312. 9p.