Suchergebnisse - "Dynamically Reconfigurable Resource Array"

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study

Autoren: Pudi, Dhilleswararao Yu, Yang Stathis, Dimitrios et al.

Quelle: IEEE Access. 12:155885-155903

Schlagwörter: Coarse grain reconfigurable architecture, field programmable gate array (FPGA), dynamically reconfigurable resource array (DRRA), distributed memory architecture (DiMArch), matrix multiplication, high-level synthesis, hardware accelerators, hardware-software co-design

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-356494
https://doi.org/10.1109/ACCESS.2024.3484175

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework

Autoren: Pudi, Dhilleswararao Malviya, Shivam Boppu, Srinivas et al.

Quelle: IEEE Access. 12:124081-124094

Schlagwörter: Random access memory, Radio frequency, Registers, Switches, Dynamic scheduling, Reconfigurable architectures, Distributed management, Memory management, Integer linear programming, Scheduling, Power demand, Coarse-grain reconfigurable architecture, dynamically reconfigurable resource array, distributed memory architecture, high-level synthesis, binding

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Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-354595
https://doi.org/10.1109/ACCESS.2024.3453503

Automating functional unit and register binding for synchoros CGRA platform

Autoren: Pudi, Dhilleswararao Tiwari, Utsav Boppu, Srinivas et al.

Quelle: Design automation for embedded systems. 28(2):155-186

Schlagwörter: Binding, Coarse-grain reconfigurable architecture, Distributed memory architecture, Dynamically reconfigurable resource array, High-level synthesis, Integer linear programming, SiLago, Vesyla

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-366798

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures *

Autoren: Pudi, Dhilleswararao Ryansh, Rajeev Goudu, Vamsi et al.

Quelle: Proceedings - 2023 26th Euromicro Conference on Digital System Design, DSD 2023. :16-23

Schlagwörter: Coarse-grained reconfigurable array, Distributed memory architecture, Dynamically reconfigurable resource array, Field programmable gate array, Sobel edge detection

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-345230

Implementation of Image Averaging on DRRA and DiMArch Architectures

Autoren: Pudi, Dhilleswararao Goudu, Vamsi Boppu, Srinivas et al.

Quelle: 2023 36TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI. :65-70

Schlagwörter: Image averaging, Coarse-grained reconfigurable architectures, Dynamically reconfigurable resource array, Distributed memory architecture

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-339588

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures

Autoren: Dhilleswararao, Pudi Ryansh, Rajeev Boppu, Srinivas et al.

Quelle: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023. :86-92

Schlagwörter: Coarse Grain Reconfigurable Architectures, Convolution, Convolutional Neural Networks, Distributed Memory Architecture, Dynamically Reconfigurable Resource Array, FPGA, Machine Learning

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-336744

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture

Autoren: Jafari, Fahimeh Li, Shuo Hemani, Ahmed

Quelle: Proceedings. :73-80

Schlagwörter: DSP application, Simulink, architecture styles, coarse grain reconfigurable architecture, decision variables, design space, dynamically reconfigurable resource array, function implementation, hierarchical configware synthesis method, hierarchical method, optimal selection, optimization algorithm, optimization problem, run-time complexity, computational complexity, optimisation, reconfigurable architectures

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-90726