Search Results - "Dynamic inter-Thread vectorization"

DITVA: Dynamic Inter-Thread Vectorization Architecture

Authors: Kalathingal, Sajith Collange, Caroline Swamy, Bharath et al.

Contributors: Kalathingal, Sajith Collange, Caroline Swamy, Bharath et al.

Source: Journal of Parallel and Distributed Computing. 120:267-281

Subject Terms: 2. Zero hunger, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Single programmultiple data, Vectorization, 0103 physical sciences, Single instruction multiple data, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Simultaneous Multi-Threading, Single program multiple data, 01 natural sciences

File Description: application/pdf

Access URL: https://hal.archives-ouvertes.fr/hal-01655904/file/Kalathingal_DITVA_JPDC18%20%281%29.pdf
https://hal.archives-ouvertes.fr/hal-01655904
https://dblp.uni-trier.de/db/journals/jpdc/jpdc120.html#KalathingalCSS18
https://www.sciencedirect.com/science/article/abs/pii/S0743731517303040
https://hal.inria.fr/hal-01655904
https://hal.archives-ouvertes.fr/hal-01655904/document

Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP

Authors: André Seznec Sylvain Collange Bharath Narasimha Swamy et al.

Source: 2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). :18-25

Access URL: https://hal.inria.fr/hal-01356202/file/Kalathingal_DITVA_SBAC16.pdf
https://hal.inria.fr/hal-01356202/document
https://hal.inria.fr/hal-01356202
https://dblp.uni-trier.de/db/conf/sbac-pad/sbac-pad2016.html#KalathingalCSS16
http://ieeexplore.ieee.org/document/7789319/
http://dblp.uni-trier.de/db/conf/sbac-pad/sbac-pad2016.html#KalathingalCSS16
https://hal.archives-ouvertes.fr/hal-01356202

Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP

Authors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Contributors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Subject Terms: [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], SPMD, Vectorization, Simultaneous Multi-Threading, SIMD

File Description: application/pdf

Access URL: https://inria.hal.science/hal-01356202v1

Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture

Authors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Contributors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Subject Terms: [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Vectorization, Simultaneous Multi-Threading, Single Program Multiple Data, Single Instruction Multiple Data

File Description: application/pdf

Access URL: https://inria.hal.science/hal-01244938v1

Transforming TLP into DLP with the dynamic inter-thread vectorization architecture

Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread

Authors: Kalathingal, Sajith

Thesis Advisors: Rennes 1, Seznec, André, Collange, Sylvain

Subject Terms: Multi-Threading simultané, SPMD, SIMD, Vectorisation dynamique, Architectures des microprocesseurs, Simultaneous Multi-Threading, Dynamic inter-Thread vectorization, Microprocessor architectures

Availability: http://www.theses.fr/2016REN1S133/document

Transforming TLP into DLP with the dynamic inter-thread vectorization architecture ; Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread

Authors: Kalathingal, Sajith Inria Rennes – Bretagne Atlantique Institut National de Recherche en Informatique et en Automatique (Inria) et al.

Contributors: Kalathingal, Sajith Inria Rennes – Bretagne Atlantique Institut National de Recherche en Informatique et en Automatique (Inria) et al.

Source: https://theses.hal.science/tel-01426915 ; Hardware Architecture [cs.AR]. Université de Rennes, 2016. English. ⟨NNT : 2016REN1S133⟩.

Subject Terms: Simultaneous Multi-Threading, SPMD, SIMD, Dynamic inter-Thread vectorization, Microprocessor architectures, Multi-Threading simultané, Vectorisation dynamique, Architectures des microprocesseurs, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: NNT: 2016REN1S133

Availability: https://theses.hal.science/tel-01426915
https://theses.hal.science/tel-01426915v3/document
https://theses.hal.science/tel-01426915v3/file/KALATHINGAL_Sajith.pdf

Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture ; Transformer le TLP en DLP par la vectorisation dynamique entre threads

Authors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Contributors: Kalathingal, Sajith Collange, Caroline Narasimha Swamy, Bharath et al.

Source: https://inria.hal.science/hal-01244938 ; [Research Report] RR-8830, Inria Rennes Bretagne Atlantique. 2015.

Subject Terms: Simultaneous Multi-Threading, Single Instruction Multiple Data, Single Program Multiple Data, Vectorization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/hal-01244938
https://inria.hal.science/hal-01244938v1/document
https://inria.hal.science/hal-01244938v1/file/RR-8830.pdf

Table of Contents.

Source: 2016 28th International Symposium on Computer Architecture & High Performance Computing (SBAC-PAD); 2016, pv-viii, 4p