Suchergebnisse - "Design Aids—Optimization General Terms Algorithms"

Fpga-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Autoren: Scott Cromar Jaeho Lee Deming Chen et al.

Weitere Verfasser: Scott Cromar Jaeho Lee Deming Chen et al.

Quelle: http://icims.csl.uiuc.edu/~dchen/research/DAC09.pdf.

Schlagwörter: B.6.3 [Hardware, Design Aids—optimization General Terms Algorithms, Design, Measurement, Performance Keywords FPGA

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.9681; http://icims.csl.uiuc.edu/~dchen/research/DAC09.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.9681
http://icims.csl.uiuc.edu/~dchen/research/DAC09.pdf

DynaTune: Circuit-Level Optimization for Timing. Speculation Considering Dynamic Path Behavior

Autoren: Lu Wan Deming Chen The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Lu Wan Deming Chen The Pennsylvania State University CiteSeerX Archives

Quelle: http://icims.csl.uiuc.edu/~dchen/research/DynaTune-iccad09.pdf.

Schlagwörter: B.6.3 [Hardware, Design Aids-- Optimization. General Terms Algorithms, Performance, Design, Experimentation Keywords Timing speculation, dual threshold voltage, throughput, BDD

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.9128

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.9128
http://icims.csl.uiuc.edu/~dchen/research/DynaTune-iccad09.pdf

False Timing Path Identification Using ATPG Techniques and Delay-Based Information

Autoren: Jing Zeng Magdy Abadir Jacob Abraham et al.

Weitere Verfasser: Jing Zeng Magdy Abadir Jacob Abraham et al.

Quelle: http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2002/papers/2002/dac02/htmfiles/sun_sgi/././pdffiles/36_2.pdf.

Schlagwörter: Design Aids–Optimization General Terms Algorithms, Performance Keywords static timing analysis, false timing paths, ATPG, timing slack

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.7808; http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2002/papers/2002/dac02/htmfiles/sun_sgi/././pdffiles/36_2.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.7808
http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2002/papers/2002/dac02/htmfiles/sun_sgi/././pdffiles/36_2.pdf

2.1p Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages

Autoren: Deming Chen Jason Cong The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Deming Chen Jason Cong The Pennsylvania State University CiteSeerX Archives

Quelle: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/islped04/pdffiles/p070.pdf.

Schlagwörter: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization General Terms Algorithms, Design, Performance Keywords Circuit clustering, low-power FPGA, dual supply voltage

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.2578

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.2578
http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/islped04/pdffiles/p070.pdf

Analysis of a Genetic Programming Algorithm for Association Studies∗

Autoren: Robin Nunkesser The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Robin Nunkesser The Pennsylvania State University CiteSeerX Archives

Quelle: http://www.cs.bham.ac.uk/~wbl/biblio/gecco2008/docs/p1259.pdf.

Schlagwörter: Categories and Subject Descriptors J.3 [Computer Applications, Life andMedical Sciences— Biology and genetics, B.6.3 [Logic Design, Design Aids— Optimization General Terms Algorithms, Experimentation, Performance Keywords Genetic Programming, association studies, logic minimiza- tion

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.559.7119; http://www.cs.bham.ac.uk/~wbl/biblio/gecco2008/docs/p1259.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.559.7119
http://www.cs.bham.ac.uk/~wbl/biblio/gecco2008/docs/p1259.pdf

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Autoren: Sarvesh Bhardwaj Sarma B. K. Vrudhula The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Sarvesh Bhardwaj Sarma B. K. Vrudhula The Pennsylvania State University CiteSeerX Archives

Quelle: http://www.cs.york.ac.uk/rts/docs/DAC-1964-2005/papers/2005/dac05/pdffiles/p541.pdf.

Schlagwörter: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—Optimization General Terms Algorithms, Design, Performance Keywords Leakage, Statistical, Optimization, Geometric Programming

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.528.436

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.528.436
http://www.cs.york.ac.uk/rts/docs/DAC-1964-2005/papers/2005/dac05/pdffiles/p541.pdf

A Synthesis Oriented Omniscient Manual Editor

Autoren: Tomasz S. Czajkowski Jonathan Rose The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Tomasz S. Czajkowski Jonathan Rose The Pennsylvania State University CiteSeerX Archives

Quelle: http://www.eecg.toronto.edu/~jayar/pubs/czajkowski/big.pdf.

Schlagwörter: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization General Terms Algorithms Keywords Synthesis, Manual, Virtex-E

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.6356; http://www.eecg.toronto.edu/~jayar/pubs/czajkowski/big.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.6356
http://www.eecg.toronto.edu/~jayar/pubs/czajkowski/big.pdf

A Computing Origami: Folding Streams in FPGAs

Autoren: Andrei Hagiescu Weng-fai Wong David F. Bacon et al.

Weitere Verfasser: Andrei Hagiescu Weng-fai Wong David F. Bacon et al.

Quelle: http://people.csail.mit.edu/rabbah/docs/hagiescu-dac-2009.pdf.

Schlagwörter: B.6.3 [Logic design, Design aids—Optimization General Terms Algorithms, Design, Performance Keywords FPGA, Streaming, Throughput, Latency

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.163.449

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.163.449
http://people.csail.mit.edu/rabbah/docs/hagiescu-dac-2009.pdf

A Computing Origami: Folding Streams in FPGAs

Autoren: Andrei Hagiescu Weng-fai Wong David F. Bacon et al.

Weitere Verfasser: Andrei Hagiescu Weng-fai Wong David F. Bacon et al.

Quelle: http://www.comp.nus.edu.sg/~wongwf/papers/DAC09_Andrei.pdf.

Schlagwörter: B.6.3 [Logic design, Design aids—Optimization General Terms Algorithms, Design, Performance Keywords FPGA, Streaming, Throughput, Latency

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.150.5786; http://www.comp.nus.edu.sg/~wongwf/papers/DAC09_Andrei.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.150.5786
http://www.comp.nus.edu.sg/~wongwf/papers/DAC09_Andrei.pdf

Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis.

Autoren: Jason Cong Peng Zhang Yi Zou

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1233-1238, 6p

Schlagwörter: MEMORY hierarchy (Computer science), BANDWIDTH allocation, HIGH-level programming languages, LOOP tiling (Computer science), NETWORK performance, INTEGRATED circuit interconnections, KNAPSACK problems

Generalized SAT-Sweeping for Post-Mapping Optimization.

Autoren: Welp, Tobias Krishnaswamy, Smita Kuehlmann, Andreas

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p814-819, 6p

Schlagwörter: MATHEMATICAL optimization, ALGORITHMS, SCIENCE & technology libraries, BOOLEAN searching, SIMULATION methods & models

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis.

Autoren: Cong, Jason Zhang, Peng Zou, Yi

Quelle: DAC Design Automation Conference 2012; 1/ 1/2012, p1229-1234, 6p

Post Sign-off Leakage Power Optimization.

Autoren: Abrishami, Hamed Lou, Jinan Qin, Jeff et al.

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p453-458, 6p, 4 Diagrams, 3 Charts, 1 Graph

Schlagwörter: COMPLEMENTARY metal oxide semiconductors, ELECTRIC power consumption, CONJUGATE gradient methods, LINEAR programming, ALGORITHMS

Node Addition and Removal in the Presence of Don't Cares.

Autoren: Yung-Chih Chen Chun-Yao Wang

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jun2010, p505-510, 6p, 5 Diagrams, 4 Charts

Schlagwörter: ATRIOVENTRICULAR node, ELECTRIC inverters, ELECTRIC circuits, BENCHMARKING (Management), REDUNDANCY in engineering

FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation.

Autoren: Cromar, Scott Jaeho Lee Deming Chen

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p838-843, 6p, 2 Diagrams, 4 Charts, 1 Graph

Schlagwörter: ALGORITHMS, ENERGY consumption, ELECTRIC power failures, APPLICATION software, SYSTEM failures

A Computing Origami: Folding Streams in FPGAs.

Autoren: Hagiescu, Andrei Weng-Fai Wong Bacon, David F. et al.

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p282-287, 6p, 5 Diagrams, 2 Charts, 2 Graphs

Schlagwörter: PARALLEL processing, LATENT variables, STREAMING technology, OPL (Computer program language), SOFT computing, SIMULTANEOUS multithreading processors

Resurrecting Infeasible Clock-Gating Functions.

Autoren: Arbel, Eli Eisner, Cindy Rokhlenko, Oleg

Quelle: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p160-165, 6p, 1 Diagram, 1 Chart

Schlagwörter: REAL-time clocks (Computers), GATE array circuits, APPROXIMATION theory, LOW voltage integrated circuits, INDUSTRIAL design

Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.

Autoren: Yu Wang Yongpan Liu Rong Luo et al.

Quelle: ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics & Design; 2006, p238-243, 6p

Active mode leakage reduction using fine-grained forward body biasing strategy.

Autoren: Khandelwal, Vishal Srivastava, Ankur

Quelle: Proceedings of the 2004 International Symposium Low Power Electronics & Design; 8/9/2004, p150-155, 6p

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.

Autoren: Chen, Deming Cong, Jason

Quelle: Proceedings of the 2004 International Symposium Low Power Electronics & Design; 8/9/2004, p70-73, 4p