Výsledky vyhľadávania - "Concurrent Programming–CSP"

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

Autori: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/dac03/pdffiles/20_3.pdf.

Predmety: B.6.1 [Logic Design, Design Styles–Asynchronous circuits, Parallel circuits, D.1.3 [Programming Techniques, Concurrent Programming–CSP, B.6.3 [Logic Design, Design Aids– Hardware description languages, Simulation, Verilog, PLI. General Terms Design, Languages. Keywords Asynchronous circuits, CSP, CHP, PLI, Channel

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.5030

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.5030
http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/dac03/pdffiles/20_3.pdf

20.3 Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction

Autori: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Arash Saifhashemi Hossein Pedram The Pennsylvania State University CiteSeerX Archives

Zdroj: http://ceit.aut.ac.ir/~pedram/Papers/Paper-DAC2003-PLI.pdf.

Predmety: B.6.1 [Logic Design, Design Styles–Asynchronous circuits, Parallel circuits, D.1.3 [Programming Techniques, Concurrent Programming–CSP, B.6.3 [Logic Design, Design Aids– Hardware description languages, Simulation, Verilog, PLI. General Terms Design, Languages. Keywords Asynchronous circuits, CSP, CHP, PLI, Channel

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.424.2587

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.424.2587
http://ceit.aut.ac.ir/~pedram/Papers/Paper-DAC2003-PLI.pdf