Suchergebnisse - "Computer Science - Hardware Architecture"

Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

Autoren: Prabodh Katti Clement Ruah Osvaldo Simeone et al.

Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 72:5422-5435

Schlagwörter: FOS: Computer and information sciences, Emerging Technologies (cs.ET), Hardware Architecture (cs.AR), Computer Science - Emerging Technologies, Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2411.07902

Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow

Autoren: Philip Wiese Gamze İslamoğlu Moritz Scherer et al.

Quelle: IEEE Design & Test. 42:63-72

Schlagwörter: FOS: Computer and information sciences, Neural Networks, TinyML, Deployment, Transformers, Accelerators, Computer Science - Machine Learning, TinyML, Transformers, Neural Networks, Deployment, Accelerators, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, 7. Clean energy, Neural networks, Machine Learning (cs.LG)

Dateibeschreibung: application/pdf

Zugangs-URL: http://arxiv.org/abs/2408.02473
https://ieeexplore.ieee.org/document/10833747
https://hdl.handle.net/11583/2996569
https://doi.org/10.1109/mdat.2025.3527371
https://hdl.handle.net/11585/1000948
https://ieeexplore.ieee.org/document/10833747
https://doi.org/10.1109/mdat.2025.3527371

ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection

Autoren: Ruisi Zhang Rachel Selina Rajarathnam David Z. Pan et al.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44:3910-3923

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2404.18407

CMD: A Cache-Assisted GPU Memory Deduplication Architecture

Autoren: Wei Zhao Dan Feng Wei Tong et al.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44:3752-3763

Schlagwörter: FOS: Computer and information sciences, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2408.09483

RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

Autoren: Yonghae Kim Anurag Kar Jaewon Lee et al.

Quelle: IEEE Transactions on Computers. 74:3291-3304

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2308.02945

A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge

Autoren: Georgios Papandroulidakis Shady Agwa Ahmet Cirakoglu et al.

Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 72:5545-5558

Schlagwörter: FOS: Computer and information sciences, Emerging Technologies (cs.ET), Hardware Architecture (cs.AR), FOS: Electrical engineering, electronic engineering, information engineering, Computer Science - Emerging Technologies, Systems and Control (eess.SY), Computer Science - Hardware Architecture, Electrical Engineering and Systems Science - Systems and Control

Zugangs-URL: http://arxiv.org/abs/2410.03414

A 5T-2MTJ STT-Assisted Spin-Orbit-Torque-Based Ternary Content Addressable Memory for Hardware Accelerators

Autoren: Siri Narla Piyush Kumar Azad Naeemi

Quelle: IEEE Transactions on Magnetics. 61:1-9

Schlagwörter: FOS: Computer and information sciences, Emerging Technologies (cs.ET), Hardware Architecture (cs.AR), Computer Science - Emerging Technologies, Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2409.17863

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products

Autoren: İslamoğlu, Gamze Bertaccini, Luca Prasad, Arpan Suravi et al.

Quelle: 2025 IEEE 36th International Conference on Application-specific Systems, Architectures and Processors (ASAP). :81-84

Schlagwörter: FOS: Computer and information sciences, Micro-scaling formats, RISC-V architectures, Low-power digital systems, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2505.13159
https://hdl.handle.net/11585/1025802
https://doi.org/10.1109/asap65064.2025.00021

LarQucut: A New Cutting and Mapping Approach for Large-sized Quantum Circuits in Distributed Quantum Computing (DQC) Environments

Autoren: Xinglei Dou Lei Liu Zhuohao Wang et al.

Quelle: ACM Transactions on Architecture and Code Optimization. 22:1-24

Schlagwörter: FOS: Computer and information sciences, Quantum Physics, Hardware Architecture (cs.AR), FOS: Physical sciences, Computer Science - Hardware Architecture, Quantum Physics (quant-ph)

Zugangs-URL: http://arxiv.org/abs/2502.21000

gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography

Autoren: Qian Xiong Weiliang Ma Xuanhua Shi et al.

Quelle: ACM Transactions on Architecture and Code Optimization. 22:1-27

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware Architecture (cs.AR), Distributed, Parallel, and Cluster Computing (cs.DC), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2501.03245

Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir

Autoren: Sosei Ikeda Hiromitsu Awano Takashi Sato

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44:3323-3335

Schlagwörter: FOS: Computer and information sciences, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2504.11970

ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory-Based Ternary LLMs

Autoren: Akul Malhotra Sumeet Kumar Gupta

Quelle: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 33:2518-2527

Schlagwörter: FOS: Computer and information sciences, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2506.01140

SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation

Autoren: Wontak Han Hyunjun Cho Donghyuk Kim et al.

Quelle: IEEE Transactions on Computers. 74:2909-2922

Schlagwörter: Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2401.17005

IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping

Autoren: Adrian Kneip Martin Lefebvre Pol Maistriaux et al.

Quelle: IEEE Transactions on Circuits and Systems for Artificial Intelligence. 2:222-235

Schlagwörter: FOS: Computer and information sciences, Artificial Intelligence (cs.AI), Computer Science - Artificial Intelligence, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2412.19750

PolyLUT: Ultra-Low Latency Polynomial Inference With Hardware-Aware Structured Pruning

Autoren: Marta Andronic Jiawen Li George A. Constantinides

Quelle: IEEE Transactions on Computers. 74:3181-3194

Schlagwörter: FOS: Computer and information sciences, Computer Science - Machine Learning, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Machine Learning (cs.LG)

Zugangs-URL: http://arxiv.org/abs/2501.08043

WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy

Autoren: Jeffry Victor Dong Eun Kim Chunguang Wang et al.

Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 72:4638-4648

Schlagwörter: FOS: Computer and information sciences, Emerging Technologies (cs.ET), Hardware Architecture (cs.AR), Computer Science - Emerging Technologies, Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/abs/2406.14706

FAULT+PROBE: A Generic Rowhammer-based Bit Recovery Attack

Autoren: Kemal Derya M. Caner Tol Berk Sunar

Quelle: Proceedings of the 20th ACM Asia Conference on Computer and Communications Security. :1219-1234

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2406.06943

EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks

Autoren: Tianhong Xu Aidong Adam Ding Yunsi Fei

Quelle: Proceedings of the 20th ACM Asia Conference on Computer and Communications Security. :1294-1308

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2504.13385

'vcd2df' - Leveraging Data Science Insights for Hardware Security Research

Autoren: Deutschbein, Calvin Ostler, Jimmy Raj, Hriday

Quelle: 2025 International Conference on Artificial Intelligence, Computer, Data Sciences and Applications (ACDSA). :1-6

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2505.06470

DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing

Autoren: Jinyan Xu Yangye Zhou Xingzhi Zhang et al.

Quelle: Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3. :64-80

Schlagwörter: FOS: Computer and information sciences, Computer Science - Cryptography and Security, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Cryptography and Security (cs.CR)

Zugangs-URL: http://arxiv.org/abs/2504.20934