Search Results - "Computer Principles and Design in Verilog HDL"

Computer Principles and Design in Verilog HDL

Authors: Yamin Li Tsinghua University Press

Resource Type: eBook.

Subjects: Computer engineering--Data processing, Verilog (Computer hardware description language)

Categories: TECHNOLOGY & ENGINEERING / Electronics / Circuits / General

Computer Arithmetic Algorithms and Implementations.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p63-110, 48p

Instruction Set Architecture and ALU Design.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p111-142, 32p

A Brief Introduction to Logic Circuits and Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p19-62, 44p

Single-Cycle CPU Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p143-169, 27p

Exceptions and Interrupts Handling and Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p170-191, 22p

Multiple-Cycle CPU Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p192-211, 20p

Design of Pipelined CPU with Precise Interrupt in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p212-265, 54p

Floating-Point Algorithms and FPU Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p266-322, 57p

Design of Pipelined CPU with FPU in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p323-352, 30p

Memory Hierarchy and Virtual Memory Management.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p353-385, 33p

Design of Pipelined CPU with Caches and TLBs in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p386-424, 39p

Multithreading CPU and Multicore CPU Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p425-442, 18p

Input/Output Interface Controller Design in Verilog HDL.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p443-508, 66p

High-Performance Computers and Interconnection Networks.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p509-535, 27p

Computer Fundamentals and Performance Evaluation.

Authors: Li, Yamin

Source: Computer Principles & Design in Verilog HDL; 2015, p1-18, 18p

A Delta Sigma Modulator-Based Stochastic Divider.

Authors: Tang, Xiaochen Liu, Shanshan Niknia, Farzad et al.

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Aug2022, Vol. 69 Issue 8, p3272-3283, 12p

Subject Terms: DIGITAL electronics, MIXED signal circuits, TECHNICAL literature

Computer Fundamentals and Performance Evaluation

Source: Computer Principles and Design in Verilog HDL ; page 1-18 ; ISBN 9781118841099 9781118841105

Availability: https://doi.org/10.1002/9781118841105.ch1
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Index

Source: Computer Principles and Design in Verilog HDL ; page 539-542 ; ISBN 9781118841099 9781118841105

Availability: https://doi.org/10.1002/9781118841105.index
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High‐Performance Computers and Interconnection Networks

Source: Computer Principles and Design in Verilog HDL ; page 509-535 ; ISBN 9781118841099 9781118841105

Availability: https://doi.org/10.1002/9781118841105.ch15
http://api.wiley.com/onlinelibrary/tdm/v1/articles/10.1002%2F9781118841105.ch15
https://onlinelibrary.wiley.com/doi/pdf/10.1002/9781118841105.ch15