Suchergebnisse - "Algorithm-hardware codesign"

Improving Scalability of Mach-Zehnder Interferometer Based Photonic Computers via Algorithm-Hardware Codesign

Autoren: Mehmet Berkay On Yun-Jhu Lee Luis El Srouji et al.

Quelle: Journal of Lightwave Technology. 42:8014-8023

HDReason: Algorithm-Hardware Codesign for Hyperdimensional Knowledge Graph Reasoning

Autoren: Chen, Hanning Ni, Yang Zakeri, Ali et al.

Schlagwörter: FOS: Computer and information sciences, Computer Science - Machine Learning, Artificial Intelligence (cs.AI), Computer Science - Artificial Intelligence, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, 7. Clean energy, Machine Learning (cs.LG)

Zugangs-URL: http://arxiv.org/abs/2403.05763

Algorithm/Hardware Codesign for Real-Time On-Satellite CNN-Based Ship Detection in SAR Imagery

Autoren: Geng Yang Jie Lei Weiying Xie et al.

Quelle: IEEE Transactions on Geoscience and Remote Sensing. 60:1-18

Schlagwörter: 0211 other engineering and technologies, 02 engineering and technology, 01 natural sciences, 0105 earth and related environmental sciences

Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning

Autoren: Hai Helen Li Qinru Qiu Haowen Fang et al.

Quelle: 2021 58th ACM/IEEE Design Automation Conference (DAC). :361-366

Schlagwörter: FOS: Computer and information sciences, Hardware Architecture (cs.AR), 0202 electrical engineering, electronic engineering, information engineering, Computer Science - Neural and Evolutionary Computing, Neural and Evolutionary Computing (cs.NE), 02 engineering and technology, Computer Science - Hardware Architecture

Zugangs-URL: http://arxiv.org/pdf/2104.10712
http://arxiv.org/abs/2104.10712
https://arxiv.org/abs/2104.10712
https://dblp.uni-trier.de/db/conf/dac/dac2021.html#FangTLMLQ21

Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning

Autoren: Fang, Haowen Taylor, Brady Li, Ziru et al.

Index Begriffe: Computer Science - Hardware Architecture, Computer Science - Neural and Evolutionary Computing, text

URL: http://arxiv.org/abs/2104.10712

ALGORITHM-HARDWARE CODESIGN OF A FAST PARALLEL ROUTING ARCHITECTURE FOR CLOS NETWORKS

Autoren: Si-Qing Zheng Ashwin Gumaste Enyue Lu

Quelle: Journal of Interconnection Networks. 11:189-210

Schlagwörter: 0508 media and communications, 05 social sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: https://www.worldscientific.com/doi/abs/10.1142/S0219265910002805
https://dblp.uni-trier.de/db/journals/join/join11.html#ZhengGL10

Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters

Autoren: Zheng, S. Q. Yang, Mei

Quelle: IEEE Transactions on Parallel and Distributed Systems. 18:84-95

Schlagwörter: Delay, Electrical and Electronics, Libraries, 02 engineering and technology, Binary trees, Electrical and Computer Engineering, 7. Clean energy, Hardware, Circuits, Round robin, Controls and Control Theory, Wire, Systems and Communications, Signal Processing, Algorithm design and analysis, 0202 electrical engineering, electronic engineering, information engineering, Timing, Switches

Zugangs-URL: http://www.ee.unlv.edu/~meiyang/publications/tpds-prra.pdf
https://www.computer.org/csdl/journal/td/2007/01/04020514/13rRUxAASVx
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004020514
https://ieeexplore.ieee.org/document/4020514/
http://www.egr.unlv.edu/~meiyang/publications/tpds-final.pdf
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000004020514
http://ieeexplore.ieee.org/document/4020514/
http://www.ee.unlv.edu/~meiyang/publications/tpds-final.pdf
https://www.computer.org/csdl/journal/td/2007/01/l0084/13rRUyYSWkz

Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design

Autoren: Chao Fang Wei Sun Aojun Zhou et al.

Quelle: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43:506-519

Schlagwörter: FOS: Computer and information sciences, Computer Science - Machine Learning, Computer Science - Artificial Intelligence, deep neural networks (DNNs), pruning, Algorithm-hardware codesign, 7. Clean energy, neural network compression, sparse training, Machine Learning (cs.LG), DNN training, Artificial Intelligence (cs.AI), Hardware Architecture (cs.AR), SDG 7 - Affordable and Clean Energy, Computer Science - Hardware Architecture, SDG 7 – Betaalbare en schone energie

Zugangs-URL: http://arxiv.org/abs/2309.13015
https://research.tue.nl/en/publications/a0a0e678-c270-4c6f-b608-68d3f66ff83f
https://doi.org/10.1109/TCAD.2023.3317789

Algorithm Hardware Codesign for High Performance Neuromorphic Computing

Autoren: Fang, Haowen

Quelle: Dissertations - ALL

Schlagwörter: Computer Engineering, Engineering

Dateibeschreibung: application/pdf

Relation: https://surface.syr.edu/etd/1381; https://surface.syr.edu/context/etd/article/2382/viewcontent/SUOA_280596134_FANG_HAOWEN_2_9_2022.pdf

Verfügbarkeit: https://surface.syr.edu/etd/1381
https://surface.syr.edu/context/etd/article/2382/viewcontent/SUOA_280596134_FANG_HAOWEN_2_9_2022.pdf

Algorithm/Hardware Codesign for Real-Time On-Satellite CNN-Based Ship Detection in SAR Imagery.

Autoren: Yang, Geng Lei, Jie Xie, Weiying et al.

Quelle: IEEE Transactions on Geoscience & Remote Sensing; Apr2022, Vol. 60, p1-18, 18p

Schlagwörter: COMPUTER software reusability, SUCCESSIVE approximation analog-to-digital converters, SYNTHETIC aperture radar, CONVOLUTIONAL neural networks, LANDSAT satellites, FIELD programmable gate arrays, GATE array circuits, ALGORITHMS

ALGORITHM-HARDWARE CODESIGN OF A FAST PARALLEL ROUTING ARCHITECTURE FOR CLOS NETWORKS.

Autoren: ZHENG, S. Q. GUMASTE, A. LU, E.

Quelle: Journal of Interconnection Networks; Sep/Dec2010, Vol. 11 Issue 3/4, p189-210, 22p, 12 Diagrams

Schlagwörter: PARALLEL algorithms, COMPUTER input-output equipment, ROUTING (Computer network management), COMPUTER networks, MULTIPROCESSORS

Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters

Autoren: Si Qing Zheng Senior Member Mei Yang et al.

Weitere Verfasser: Si Qing Zheng Senior Member Mei Yang et al.

Quelle: http://www.ee.unlv.edu/~meiyang/publications/tpds-prra.pdf.

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.408.5770

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.408.5770
http://www.ee.unlv.edu/~meiyang/publications/tpds-prra.pdf

Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters.

Autoren: Si Qing Zheng Mei Yang

Quelle: IEEE Transactions on Parallel & Distributed Systems; Jan2007, Vol. 18 Issue 1, p84-95, 12p, 18 Diagrams, 4 Charts

Schlagwörter: ALGORITHMS, COMPUTER programming, NETWORK routers, BINARY number system, COMPUTER simulation, COMPUTER networks

Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review

Autoren: Shuvo, Md Maruf Hossain Islam, Syed Kamrul Cheng, Jianlin et al.

Schlagwörter: Algorithm-hardware codesign, artificial intelligence (AI), artificial intelligence on edge (edge-AI), deep learning (DL), model compression, neural accelerator

Dateibeschreibung: application/pdf

Relation: Shuvo, M.M.H., Islam, S.K., Cheng, J., & Morshed, B.I. 2023. Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review. Proceedings of the IEEE, 111(1). https://doi.org/10.1109/JPROC.2022.3226481; https://doi.org/10.1109/JPROC.2022.3226481; https://hdl.handle.net/2346/93019

Verfügbarkeit: https://hdl.handle.net/2346/93019
https://doi.org/10.1109/JPROC.2022.3226481

Accelerating ViT Inference on FPGA through Static and Dynamic Pruning

Autoren: Parikh, Dhruv Li, Shouyi Zhang, Bingyi et al.

Index Begriffe: Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Hardware Architecture, Computer Science - Computer Vision and Pattern Recognition, text

URL: http://arxiv.org/abs/2403.14047

PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System

Autoren: Rhyner, Steve Luo, Haocong Gómez-Luna, Juan et al.

Index Begriffe: Computer Science - Hardware Architecture, Computer Science - Artificial Intelligence, Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Machine Learning, text

URL: http://arxiv.org/abs/2404.07164

A High-Precision Hybrid Floating-Point Compute-in-Memory Architecture for Complex Deep Learning.

Autoren: Ma, Zizhao Wang, Chunshan Chen, Qi et al.

Quelle: Electronics (2079-9292); Nov2025, Vol. 14 Issue 22, p4414, 22p

Schlagwörter: DEEP learning, TRANSFORMER models, ENERGY consumption, IMAGE recognition (Computer vision), FLOATING-point arithmetic, CALIBRATION, MATRIX multiplications

Filter-Wise Mask Pruning and FPGA Acceleration for Object Classification and Detection.

Autoren: He, Wenjing Mei, Shaohui Hu, Jian et al.

Quelle: Remote Sensing; Nov2025, Vol. 17 Issue 21, p3582, 27p

Schlagwörter: CONVOLUTIONAL neural networks, FIELD programmable gate arrays, REAL-time computing, OBJECT recognition (Computer vision), REMOTE sensing

Robotic computing system and embodied AI evolution: an algorithm-hardware co-design perspective.

Autoren: Yan, Longke Zhao, Xin Yang, Bohan et al.

Quelle: Journal of Semiconductors; 2025, Vol. 46 Issue 10, p1-18, 18p

Maritime remote sensing ship detection in UAV image via contextual feature-guided shared convolutional networks.

Autoren: Miao, Huijie Zhang, Jie Yan, Jiang et al.

Quelle: Complex & Intelligent Systems; Oct2025, Vol. 11 Issue 10, p1-20, 20p