Výsledky vyhledávání - "ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids"

High-Level Synthesis of Pipelined FSM from Loop Nests

Autoři: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Zdroj: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

Témata: High-level synthesis, fine-grain loop optimization, control automaton, pipeline, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: 8900

Dostupnost: https://inria.hal.science/hal-01301334
https://inria.hal.science/hal-01301334v2/document
https://inria.hal.science/hal-01301334v2/file/RR-8900.pdf

High-Level Synthesis of Pipelined FSM from Loop Nests

Autoři: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Zdroj: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

Témata: pipeline, control automaton, fine-grain loop optimization, High-level synthesis, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: 8900

Dostupnost: https://inria.hal.science/hal-01301334
https://inria.hal.science/hal-01301334v2/document
https://inria.hal.science/hal-01301334v2/file/RR-8900.pdf

High-Level Synthesis of Pipelined FSM from Loop Nests

Autoři: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Zdroj: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

Témata: High-level synthesis, fine-grain loop optimization, control automaton, pipeline, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: 8900

Dostupnost: https://inria.hal.science/hal-01301334
https://inria.hal.science/hal-01301334v2/document
https://inria.hal.science/hal-01301334v2/file/RR-8900.pdf

High-Level Synthesis of Pipelined FSM from Loop Nests

Autoři: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Rastello, Fabrice Plesco, Alexandru a další

Zdroj: https://hal.inria.fr/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

Témata: High-level synthesis, fine-grain loop optimization, control automaton, pipeline, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: 8900; hal-01301334; https://hal.inria.fr/hal-01301334; https://hal.inria.fr/hal-01301334v2/document; https://hal.inria.fr/hal-01301334v2/file/RR-8900.pdf

Dostupnost: https://hal.inria.fr/hal-01301334
https://hal.inria.fr/hal-01301334v2/document
https://hal.inria.fr/hal-01301334v2/file/RR-8900.pdf

From filters to transistors A library of analog schematic with automated sizing Team: FOSS EDA for analog and mixed circuit design

Autoři: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) a další

Přispěvatelé: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) a další

Zdroj: Free Silicon Conference ; https://hal.sorbonne-universite.fr/hal-02316744 ; Free Silicon Conference, LIP6, Mar 2019, Paris, France

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Geografické téma: Paris, France

Dostupnost: https://hal.sorbonne-universite.fr/hal-02316744

RISC-V design using Free Open Source Software

Autoři: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Přispěvatelé: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Zdroj: the RISC-V Week ; https://hal.sorbonne-universite.fr/hal-02316711 ; the RISC-V Week, Oct 2019, Paris, France

Témata: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.5: Microprocessors and microcomputers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids/B.7.2.2: Placement and routing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Geografické téma: Paris, France

Dostupnost: https://hal.sorbonne-universite.fr/hal-02316711

RISC-V design using Free Open Source Software

Autoři: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Přispěvatelé: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Zdroj: the RISC-V Week ; https://hal.sorbonne-universite.fr/hal-02316711 ; the RISC-V Week, Oct 2019, Paris, France

Témata: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.5: Microprocessors and microcomputers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids/B.7.2.2: Placement and routing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Geografické téma: Paris, France

Relation: hal-02316711; https://hal.sorbonne-universite.fr/hal-02316711

Dostupnost: https://hal.sorbonne-universite.fr/hal-02316711

From filters to transistors A library of analog schematic with automated sizing Team: FOSS EDA for analog and mixed circuit design

Autoři: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) a další

Přispěvatelé: Porte, Jacky Louërat, Marie-Minerve Circuits Intégrés Numériques et Analogiques (CIAN) a další

Zdroj: Free Silicon Conference ; https://hal.sorbonne-universite.fr/hal-02316744 ; Free Silicon Conference, LIP6, Mar 2019, Paris, France

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Geografické téma: Paris, France

Relation: hal-02316744; https://hal.sorbonne-universite.fr/hal-02316744

Dostupnost: https://hal.sorbonne-universite.fr/hal-02316744

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autoři: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autoři: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Autoři: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://hal.inria.fr/hal-00747721 ; Journal of Low Power Electronics, American Scientific Publishers, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: hal-00747721; https://hal.inria.fr/hal-00747721

Dostupnost: https://hal.inria.fr/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159