Výsledky vyhľadávania - "ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS"

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Autori: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Prispievatelia: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Zdroj: https://hal.science/hal-02732902 ; 2020.

Predmety: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Dostupnosť: https://hal.science/hal-02732902
https://hal.science/hal-02732902v1/document
https://hal.science/hal-02732902v1/file/LEGO4TALK_EDP_Calculations.pdf

NoC-Based Protection for SoC Time-Driven Attacks

Autori: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius a ďalší

Prispievatelia: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius a ďalší

Zdroj: IEEE Embedded Systems Letters. 7:7-10

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Channel leakage, multiport memory, common bus, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), 02 engineering and technology, 3. Good health, Network On Chip, crossbar switch), Security, 0202 electrical engineering, electronic engineering, information engineering, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

Prístupová URL adresa: https://hal.archives-ouvertes.fr/hal-01083270
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6994256
https://hal.inria.fr/hal-01253500
http://ieeexplore.ieee.org/document/6994256
https://ieeexplore.ieee.org/document/6994256
https://dblp.uni-trier.de/db/journals/esl/esl7.html#SepulvedaDSG15

An Overflow Free Fixed-point Eigenvalue Decomposition Algorithm: Case Study of Dimensionality Reduction in Hyperspectral Images

Autori: Kabi, Bibek Sahadevan, Anand S Pradhan, Tapan a ďalší

Prispievatelia: Kabi, Bibek Sahadevan, Anand S Pradhan, Tapan a ďalší

Zdroj: 2017 Conference On Design And Architectures For Signal And Image Processing (DASIP).
https://inria.hal.science/hal-01635958
2017 Conference On Design And Architectures For Signal And Image Processing (DASIP). , 〈http://dasip2017.esit.rub.de/〉, Sep 2017, Dresden, Germany
http://dasip2017.esit.rub.de/program.html

Predmety: Affine arithmetic, fixed-point arithmetic, overflow, interval arithmetic, integer bit-width alloca- tion, formal methods, range analysis, satisfiability- modulo-theory, tion, eigenvalue decomposition, Index Terms— Affine arithmetic, integer bit-width alloca-, modulo-theory, satisfiability-, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Dresden, Germany

Dostupnosť: https://inria.hal.science/hal-01635958
https://inria.hal.science/hal-01635958v1/document
https://inria.hal.science/hal-01635958v1/file/1711.10600.pdf

Applied Reconfigurable Computing. Architectures, Tools, and Applications ; Applied Reconfigurable Computing. Architectures, Tools, and Applications: 17th International Symposium, ARC 2021

Autori: Chillet, Daniel Derrien, Steven Hannig, Frank a ďalší

Prispievatelia: Chillet, Daniel Derrien, Steven Hannig, Frank a ďalší

Zdroj: ARC 2021 - 17th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications ; https://inria.hal.science/hal-03315772 ; ARC 2021 - 17th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications, 12700, Springer, pp.1-338, 2021, LNCS, 978-3-030-79025-7. ⟨10.1007/978-3-030-79025-7⟩

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-03315772
https://doi.org/10.1007/978-3-030-79025-7

An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter

Autori: Teymourzadeh, Rozita Universiti Kebangsaan Malaysia (UKM) Faculty Of Education, Universiti Kebangsaan Malaysia (ukm), Malaysia

Prispievatelia: Teymourzadeh, Rozita Universiti Kebangsaan Malaysia (UKM) Faculty Of Education, Universiti Kebangsaan Malaysia (ukm), Malaysia

Zdroj: IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815 ; https://hal.archives-ouvertes.fr/hal-01800578 ; IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815, 2006, Kuala Lumpur, Malaysia

Predmety: ACM: D.: Software, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES, ACM: G.: Mathematics of Computing, ACM: H.: Information Systems, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-CC]Computer Science [cs]/Computational Complexity [cs.CC]

Geografické téma: Kuala Lumpur, Malaysia

Relation: hal-01800578; https://hal.archives-ouvertes.fr/hal-01800578; https://hal.archives-ouvertes.fr/hal-01800578/document; https://hal.archives-ouvertes.fr/hal-01800578/file/2005%20An%20Enhancement%20of%20Decimation%20Process%20using%20Fast%20Cascaded%20Integrator%20Comb%20%28CIC%29%20Filter.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01800578
https://hal.archives-ouvertes.fr/hal-01800578/document
https://hal.archives-ouvertes.fr/hal-01800578/file/2005%20An%20Enhancement%20of%20Decimation%20Process%20using%20Fast%20Cascaded%20Integrator%20Comb%20%28CIC%29%20Filter.pdf

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autori: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Predmety: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

Dynamic Run-time Hardware/Software Scheduling For 3D Reconfigurable SoC

Autori: Khuat, Quang Hai Chillet, Daniel Hubner, Michael a ďalší

Prispievatelia: Khuat, Quang Hai Chillet, Daniel Hubner, Michael a ďalší

Zdroj: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014) ; https://inria.hal.science/hal-01097509 ; International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Dec 2014, Cancun, Mexico

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Cancun, Mexico

Dostupnosť: https://inria.hal.science/hal-01097509

Architectures reconfigurables FPGA

Autori: Sentieys, Olivier Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) a ďalší

Prispievatelia: Sentieys, Olivier Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) a ďalší

Zdroj: Technologies logicielles Architectures des systèmes ; https://inria.hal.science/hal-00716772 ; Techniques de l'Ingénieur. Technologies logicielles Architectures des systèmes, H 1 196, Techniques de l'Ingénieur, pp.1-22, 2012

Predmety: ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Dostupnosť: https://inria.hal.science/hal-00716772

UPaRC: Ultra-Fast Power-aware Reconfiguration Controller

Autori: Bonamy, Robin Pham, Hung-Manh Pillement, Sébastien a ďalší

Prispievatelia: Bonamy, Robin Pham, Hung-Manh Pillement, Sébastien a ďalší

Zdroj: Design, Automation and Test in Europe Conference ; https://inria.hal.science/hal-00741606 ; Design, Automation and Test in Europe Conference, Mar 2012, Dresden, Germany. pp.1373-1378

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS

Geografické téma: Dresden, Germany

Dostupnosť: https://inria.hal.science/hal-00741606

Spatio-Temporal Scheduling for 3D Reconfigurable and Multiprocessor Architecture

Autori: Khuat, Quang Hai Le, Quang Hoa Chillet, Daniel a ďalší

Prispievatelia: Khuat, Quang Hai Le, Quang Hoa Chillet, Daniel a ďalší

Zdroj: Manifestation des Jeunes Chercheurs en Sciences et Technologies de l'Information et de la Communication ; https://inria.hal.science/hal-00741612 ; Manifestation des Jeunes Chercheurs en Sciences et Technologies de l'Information et de la Communication, Oct 2012, Lille, France

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS

Geografické téma: Lille, France

Dostupnosť: https://inria.hal.science/hal-00741612

Spatio-Temporal Scheduling for 3D Reconfigurable \& Multiprocessor Architecture

Autori: Khuat, Quang Hai Le, Quang Hoa Chillet, Daniel a ďalší

Prispievatelia: Khuat, Quang Hai Le, Quang Hoa Chillet, Daniel a ďalší

Zdroj: International Design and Test Symposium, IDT 2012 ; https://inria.hal.science/hal-00753902 ; International Design and Test Symposium, IDT 2012, University at Qatar, Dec 2012, Doha, Qatar

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS

Geografické téma: Doha, Qatar

Dostupnosť: https://inria.hal.science/hal-00753902

Circuits électroniques pour la génération de nombres aléatoires

Autori: Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique a ďalší

Prispievatelia: Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique a ďalší

Zdroj: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://inria.hal.science/hal-01061471 ; Techniques de l'Ingénieur, 2014, H5215.

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-01061471