Výsledky vyhledávání - "ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization"

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  1. 1

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  2. 2

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  3. 3

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: Automatic Parallelization, Compilation Techniques, High-Level Synthesis, FPGA, Synthèse haut-niveau, Parallélisation automatique, Compilation, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  4. 4

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Laboratoire de l'Informatique du Parallélisme (LIP) a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Laboratoire de l'Informatique du Parallélisme (LIP) a další

    Zdroj: https://hal.inria.fr/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Relation: tel-02151877; https://hal.inria.fr/tel-02151877; https://hal.inria.fr/tel-02151877v2/document; https://hal.inria.fr/tel-02151877v2/file/hdr-alias.pdf

    Dostupnost: https://hal.inria.fr/tel-02151877
    https://hal.inria.fr/tel-02151877v2/document
    https://hal.inria.fr/tel-02151877v2/file/hdr-alias.pdf

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  5. 5

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Zdroj: https://hal.inria.fr/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Relation: tel-02151877; https://hal.inria.fr/tel-02151877; https://hal.inria.fr/tel-02151877/document; https://hal.inria.fr/tel-02151877/file/hdr-alias.pdf

    Dostupnost: https://hal.inria.fr/tel-02151877
    https://hal.inria.fr/tel-02151877/document
    https://hal.inria.fr/tel-02151877/file/hdr-alias.pdf

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  6. 6

    A semiempirical model for wakeup time estimation in power-gated logic clusters

    Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

    Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: San Fransisco, United States

    Dostupnost: https://inria.hal.science/hal-00752606

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  7. 7

    A semiempirical model for wakeup time estimation in power-gated logic clusters

    Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

    Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: San Fransisco, United States

    Dostupnost: https://inria.hal.science/hal-00752606

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  8. 8

    A semiempirical model for wakeup time estimation in power-gated logic clusters

    Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

    Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: San Fransisco, United States

    Dostupnost: https://inria.hal.science/hal-00752606

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  9. 9

    A semiempirical model for wakeup time estimation in power-gated logic clusters

    Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

    Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://hal.inria.fr/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

    Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: San Fransisco, United States

    Relation: hal-00752606; https://hal.inria.fr/hal-00752606

    Dostupnost: https://hal.inria.fr/hal-00752606

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