Výsledky vyhledávání - "ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis"

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  1. 1

    Model Driven Engineering Benefits for High Level Synthesis

    Autoři: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

    Přispěvatelé: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

    Zdroj: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

    Témata: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Dostupnost: https://inria.hal.science/inria-00311300
    https://inria.hal.science/inria-00311300/document
    https://inria.hal.science/inria-00311300/file/RR-6615.pdf

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  2. 2

    Model Driven Engineering Benefits for High Level Synthesis

    Autoři: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

    Přispěvatelé: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc a další

    Zdroj: https://hal.inria.fr/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

    Témata: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Relation: Report N°: RR-6615; inria-00311300; https://hal.inria.fr/inria-00311300; https://hal.inria.fr/inria-00311300/document; https://hal.inria.fr/inria-00311300/file/RR-6615.pdf

    Dostupnost: https://hal.inria.fr/inria-00311300
    https://hal.inria.fr/inria-00311300/document
    https://hal.inria.fr/inria-00311300/file/RR-6615.pdf

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  3. 3

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  4. 4

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  5. 5

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a další

    Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: Automatic Parallelization, Compilation Techniques, High-Level Synthesis, FPGA, Synthèse haut-niveau, Parallélisation automatique, Compilation, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Dostupnost: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  6. 6

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Laboratoire de l'Informatique du Parallélisme (LIP) a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Laboratoire de l'Informatique du Parallélisme (LIP) a další

    Zdroj: https://hal.inria.fr/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Relation: tel-02151877; https://hal.inria.fr/tel-02151877; https://hal.inria.fr/tel-02151877v2/document; https://hal.inria.fr/tel-02151877v2/file/hdr-alias.pdf

    Dostupnost: https://hal.inria.fr/tel-02151877
    https://hal.inria.fr/tel-02151877v2/document
    https://hal.inria.fr/tel-02151877v2/file/hdr-alias.pdf

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  7. 7

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Autoři: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Přispěvatelé: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Inria Grenoble - Rhône-Alpes a další

    Zdroj: https://hal.inria.fr/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Témata: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Relation: tel-02151877; https://hal.inria.fr/tel-02151877; https://hal.inria.fr/tel-02151877/document; https://hal.inria.fr/tel-02151877/file/hdr-alias.pdf

    Dostupnost: https://hal.inria.fr/tel-02151877
    https://hal.inria.fr/tel-02151877/document
    https://hal.inria.fr/tel-02151877/file/hdr-alias.pdf

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  8. 8

    Global Optimization based on Contractor Programming ; Global Optimization based on Contractor Programming: Application to $H_\infty$ synthesis

    Autoři: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Přispěvatelé: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Zdroj: 8th Small Workshop on Interval Methods
    https://hal.science/hal-01194756
    8th Small Workshop on Interval Methods, Jun 2015, Prague, Czech Republic
    http://kam.mff.cuni.cz/conferences/swim2015/

    Témata: Contractor Programming, Global Optimization, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.6: Optimization/G.1.6.2: Global optimization, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, [INFO.INFO-RO]Computer Science [cs]/Operations Research [math.OC], [MATH.MATH-OC]Mathematics [math]/Optimization and Control [math.OC]

    Geografické téma: Prague, Czech Republic

    Dostupnost: https://hal.science/hal-01194756

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  9. 9

    Global Optimization based on Contractor Programming ; Global Optimization based on Contractor Programming: Application to $H_\infty$ synthesis

    Autoři: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Přispěvatelé: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Zdroj: 8th Small Workshop on Interval Methods
    https://hal.science/hal-01194756
    8th Small Workshop on Interval Methods, Jun 2015, Prague, Czech Republic
    http://kam.mff.cuni.cz/conferences/swim2015/

    Témata: Contractor Programming, Global Optimization, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.6: Optimization/G.1.6.2: Global optimization, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, [INFO.INFO-RO]Computer Science [cs]/Operations Research [math.OC], [MATH.MATH-OC]Mathematics [math]/Optimization and Control [math.OC]

    Geografické téma: Prague, Czech Republic

    Dostupnost: https://hal.science/hal-01194756

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  10. 10

    Global Optimization based on Contractor Programming ; Global Optimization based on Contractor Programming: Application to $H_\infty$ synthesis

    Autoři: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Přispěvatelé: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Zdroj: 8th Small Workshop on Interval Methods
    https://hal.science/hal-01194756
    8th Small Workshop on Interval Methods, Jun 2015, Prague, Czech Republic
    http://kam.mff.cuni.cz/conferences/swim2015/

    Témata: Global Optimization, Contractor Programming, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.6: Optimization/G.1.6.2: Global optimization, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, [INFO.INFO-RO]Computer Science [cs]/Operations Research [math.OC], [MATH.MATH-OC]Mathematics [math]/Optimization and Control [math.OC]

    Geografické téma: Prague, Czech Republic

    Dostupnost: https://hal.science/hal-01194756

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  11. 11

    Global Optimization based on Contractor Programming ; Global Optimization based on Contractor Programming: Application to $H_\infty$ synthesis

    Autoři: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Přispěvatelé: Ninin, Jordan Monnet, Dominique Clement, Benoit a další

    Zdroj: 8th Small Workshop on Interval Methods
    https://hal.archives-ouvertes.fr/hal-01194756
    8th Small Workshop on Interval Methods, Jun 2015, Prague, Czech Republic
    http://kam.mff.cuni.cz/conferences/swim2015/

    Témata: Contractor Programming, Global Optimization, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.6: Optimization/G.1.6.2: Global optimization, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, [INFO.INFO-RO]Computer Science [cs]/Operations Research [cs.RO], [MATH.MATH-OC]Mathematics [math]/Optimization and Control [math.OC]

    Geografické téma: Prague, Czech Republic

    Relation: hal-01194756; https://hal.archives-ouvertes.fr/hal-01194756

    Dostupnost: https://hal.archives-ouvertes.fr/hal-01194756

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