Výsledky vyhľadávania - "ACM: B.: Hardware/B.6: LOGIC DESIGN"

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Autori: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Prispievatelia: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Zdroj: https://hal.science/hal-02732902 ; 2020.

Predmety: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Dostupnosť: https://hal.science/hal-02732902
https://hal.science/hal-02732902v1/document
https://hal.science/hal-02732902v1/file/LEGO4TALK_EDP_Calculations.pdf

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Autori: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Prispievatelia: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Zdroj: https://hal.science/hal-02732902 ; 2020.

Predmety: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Dostupnosť: https://hal.science/hal-02732902
https://hal.science/hal-02732902v1/document
https://hal.science/hal-02732902v1/file/LEGO4TALK_EDP_Calculations.pdf

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Autori: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Prispievatelia: O'Connor, Ian Stanojevic, Zlatan Baumgartner, Oskar a ďalší

Zdroj: https://hal.archives-ouvertes.fr/hal-02732902 ; 2020.

Predmety: ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Relation: hal-02732902; https://hal.archives-ouvertes.fr/hal-02732902; https://hal.archives-ouvertes.fr/hal-02732902/document; https://hal.archives-ouvertes.fr/hal-02732902/file/LEGO4TALK_EDP_Calculations.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-02732902
https://hal.archives-ouvertes.fr/hal-02732902/document
https://hal.archives-ouvertes.fr/hal-02732902/file/LEGO4TALK_EDP_Calculations.pdf

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autori: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Prispievatelia: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Predmety: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Dostupnosť: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autori: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Prispievatelia: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Predmety: SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, Information Flow Tracking, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Dostupnosť: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autori: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Prispievatelia: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Predmety: SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, Information Flow Tracking, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Dostupnosť: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autori: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Prispievatelia: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.science/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Predmety: SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, Information Flow Tracking, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Dostupnosť: https://hal.science/hal-01558473
https://hal.science/hal-01558473v1/document
https://hal.science/hal-01558473v1/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Autori: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Prispievatelia: Wahab, Muhammad Abdul Cotret, Pascal Nasr Allah, Mounir a ďalší

Zdroj: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
https://hal.archives-ouvertes.fr/hal-01558473
2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
https://www.fpl2017.org/

Predmety: Information Flow Tracking, SoC, Zynq, Zynq SoC, CoreSight, ARM Debug components, IFT, Dynamic information flow tracking, DIFT, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Ghent, Belgium

Relation: hal-01558473; https://hal.archives-ouvertes.fr/hal-01558473; https://hal.archives-ouvertes.fr/hal-01558473/document; https://hal.archives-ouvertes.fr/hal-01558473/file/bare_conf.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01558473
https://hal.archives-ouvertes.fr/hal-01558473/document
https://hal.archives-ouvertes.fr/hal-01558473/file/bare_conf.pdf
https://doi.org/10.23919/fpl.2017.8056767

Novel Architecture of Smart FFT Processor

Autori: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Prispievatelia: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Zdroj: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Predmety: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter

Autori: Teymourzadeh, Rozita Universiti Kebangsaan Malaysia (UKM) Faculty Of Education, Universiti Kebangsaan Malaysia (ukm), Malaysia

Prispievatelia: Teymourzadeh, Rozita Universiti Kebangsaan Malaysia (UKM) Faculty Of Education, Universiti Kebangsaan Malaysia (ukm), Malaysia

Zdroj: IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815 ; https://hal.archives-ouvertes.fr/hal-01800578 ; IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815, 2006, Kuala Lumpur, Malaysia

Predmety: ACM: D.: Software, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES, ACM: G.: Mathematics of Computing, ACM: H.: Information Systems, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-CC]Computer Science [cs]/Computational Complexity [cs.CC]

Geografické téma: Kuala Lumpur, Malaysia

Relation: hal-01800578; https://hal.archives-ouvertes.fr/hal-01800578; https://hal.archives-ouvertes.fr/hal-01800578/document; https://hal.archives-ouvertes.fr/hal-01800578/file/2005%20An%20Enhancement%20of%20Decimation%20Process%20using%20Fast%20Cascaded%20Integrator%20Comb%20%28CIC%29%20Filter.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01800578
https://hal.archives-ouvertes.fr/hal-01800578/document
https://hal.archives-ouvertes.fr/hal-01800578/file/2005%20An%20Enhancement%20of%20Decimation%20Process%20using%20Fast%20Cascaded%20Integrator%20Comb%20%28CIC%29%20Filter.pdf

Dynamic Variable Stage Pipeline: an Implementation of its Control

Autori: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a ďalší

Zdroj: https://inria.hal.science/inria-00381563 ; [Research Report] RR-6918, INRIA. 2009, pp.15.

Predmety: Variable length pipeline, Variable stage pipeline, Pipeline stage unification, Low Power, Leakage, Energy, Throughput, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnosť: https://inria.hal.science/inria-00381563
https://inria.hal.science/inria-00381563v1/document
https://inria.hal.science/inria-00381563v1/file/RR-6918.pdf

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autori: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Predmety: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autori: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Predmety: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644/document
https://inria.hal.science/inria-00381644/file/RR-6919.pdf

Dynamic Variable Stage Pipeline: an Implementation of its Control

Autori: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony Models and methods of analysis and optimization for systems with real-time and embedding constraints (AOSTE) a ďalší

Zdroj: https://hal.inria.fr/inria-00381563 ; [Research Report] RR-6918, INRIA. 2009, pp.15.

Predmety: Variable length pipeline, Variable stage pipeline, Pipeline stage unification, Low Power, Leakage, Energy, Throughput, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Relation: Report N°: RR-6918; inria-00381563; https://hal.inria.fr/inria-00381563; https://hal.inria.fr/inria-00381563/document; https://hal.inria.fr/inria-00381563/file/RR-6918.pdf

Dostupnosť: https://hal.inria.fr/inria-00381563
https://hal.inria.fr/inria-00381563/document
https://hal.inria.fr/inria-00381563/file/RR-6918.pdf

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autori: Boucaron, Julien Coadou, Anthony De Simone, Robert a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony De Simone, Robert a ďalší

Zdroj: https://hal.inria.fr/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Predmety: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: RR-6919; inria-00381644; https://hal.inria.fr/inria-00381644; https://hal.inria.fr/inria-00381644/document; https://hal.inria.fr/inria-00381644/file/RR-6919.pdf

Dostupnosť: https://hal.inria.fr/inria-00381644
https://hal.inria.fr/inria-00381644/document
https://hal.inria.fr/inria-00381644/file/RR-6919.pdf

La réalisation des opérateurs logiques

Autori: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Prispievatelia: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Zdroj: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793651 ; 2017.

Predmety: mémoires RAM, technologies CMOS, circuits CMOS | circuits ASIC, puissance et énergie, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://hal.science/hal-01793651

La réalisation des opérateurs logiques

Autori: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Prispievatelia: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Zdroj: Techniques de l'Ingenieur ; https://hal.archives-ouvertes.fr/hal-01793651 ; 2017

Predmety: puissance et énergie, circuits CMOS | circuits ASIC, mémoires RAM, technologies CMOS, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: hal-01793651; https://hal.archives-ouvertes.fr/hal-01793651

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01793651