Výsledky vyhľadávania - "ACM: B.: Hardware/B.3: MEMORY STRUCTURES"

A Band-pass Prefetching : An Effective Prefetch Management Mechanism using Prefetch-fraction Metric in Multi-core Systems

Autori: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Prispievatelia: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Zdroj: ISSN: 1544-3566.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-01519648
https://inria.hal.science/hal-01519648v1/document
https://inria.hal.science/hal-01519648v1/file/Band-passPrefetching_CameraReady.pdf

Dynamic and Discrete Cache Insertion Policies for Managing Shared Last Level Caches in Large Multicores

Autori: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Prispievatelia: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Zdroj: ISSN: 0743-7315.

Predmety: Footprint-number, Discrete priorities, More cores than associativity, Bypassing, Cache management, Shared resource, ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-01519650
https://inria.hal.science/hal-01519650v1/document
https://inria.hal.science/hal-01519650v1/file/procs-template%20%281%29.pdf
https://doi.org/10.1016/j.jpdc.2017.02.004

Dynamic and Discrete Cache Insertion Policies for Managing Shared Last Level Caches in Large Multicores

Autori: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Prispievatelia: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Zdroj: ISSN: 0743-7315.

Predmety: Shared resource, Cache management, Bypassing, More cores than associativity, Discrete priorities, Footprint-number, ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-01519650
https://inria.hal.science/hal-01519650v1/document
https://inria.hal.science/hal-01519650v1/file/procs-template%20%281%29.pdf
https://doi.org/10.1016/j.jpdc.2017.02.004

A Band-pass Prefetching : An Effective Prefetch Management Mechanism using Prefetch-fraction Metric in Multi-core Systems

Autori: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Prispievatelia: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Zdroj: ISSN: 1544-3566.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/hal-01519648
https://inria.hal.science/hal-01519648v1/document
https://inria.hal.science/hal-01519648v1/file/Band-passPrefetching_CameraReady.pdf

A Band-pass Prefetching : An Effective Prefetch Management Mechanism using Prefetch-fraction Metric in Multi-core Systems

Autori: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Prispievatelia: Sridharan, Aswinkumar Panda, Biswabandan Seznec, André a ďalší

Zdroj: ISSN: 1544-3566.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: hal-01519648; https://hal.inria.fr/hal-01519648; https://hal.inria.fr/hal-01519648/document; https://hal.inria.fr/hal-01519648/file/Band-passPrefetching_CameraReady.pdf

Dostupnosť: https://hal.inria.fr/hal-01519648
https://hal.inria.fr/hal-01519648/document
https://hal.inria.fr/hal-01519648/file/Band-passPrefetching_CameraReady.pdf

Dynamic and Discrete Cache Insertion Policies for Managing Shared Last Level Caches in Large Multicores

Autori: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Prispievatelia: Sridharan, Aswinkumar Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) a ďalší

Zdroj: ISSN: 0743-7315.

Predmety: Shared resource, Cache management, Bypassing, Footprint-number, Discrete priorities, More cores than associativity, ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: hal-01519650; https://hal.inria.fr/hal-01519650; https://hal.inria.fr/hal-01519650/document; https://hal.inria.fr/hal-01519650/file/procs-template%20%281%29.pdf

Dostupnosť: https://hal.inria.fr/hal-01519650
https://hal.inria.fr/hal-01519650/document
https://hal.inria.fr/hal-01519650/file/procs-template%20%281%29.pdf
https://doi.org/10.1016/j.jpdc.2017.02.004

Towards Phase Change Memory as a Secure Main Memory

Autori: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique a ďalší

Prispievatelia: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique a ďalší

Zdroj: https://inria.hal.science/inria-00430010 ; [Research Report] RR-7088, INRIA. 2009, pp.13.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.0: General, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00430010
https://inria.hal.science/inria-00430010v2/document
https://inria.hal.science/inria-00430010v2/file/PCMsecur-new.pdf

Towards Phase Change Memory as a Secure Main Memory

Autori: Seznec, André Amdahl's Law is Forever (ALF) Centre Inria de l'Université de Rennes a ďalší

Prispievatelia: Seznec, André Amdahl's Law is Forever (ALF) Centre Inria de l'Université de Rennes a ďalší

Zdroj: https://inria.hal.science/inria-00430010 ; [Research Report] RR-7088, INRIA. 2009, pp.13.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.0: General, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00430010
https://inria.hal.science/inria-00430010v2/document
https://inria.hal.science/inria-00430010v2/file/PCMsecur-new.pdf

Towards Phase Change Memory as a Secure Main Memory

Autori: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique a ďalší

Prispievatelia: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique a ďalší

Zdroj: https://hal.inria.fr/inria-00430010 ; [Research Report] RR-7088, INRIA. 2009, pp.13.

Predmety: ACM: B.: Hardware, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES/B.3.0: General, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: RR-7088; inria-00430010; https://hal.inria.fr/inria-00430010; https://hal.inria.fr/inria-00430010v2/document; https://hal.inria.fr/inria-00430010v2/file/PCMsecur-new.pdf

Dostupnosť: https://hal.inria.fr/inria-00430010
https://hal.inria.fr/inria-00430010v2/document
https://hal.inria.fr/inria-00430010v2/file/PCMsecur-new.pdf

A Timing Assumption and two $t$-Resilient Protocols for Implementing an Eventual Leader Service in Asynchronous Shared Memory Systems

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://inria.hal.science/inria-00142865 ; [Research Report] PI 1842, 2007, pp.19.

Predmety: Asynchronous system, Atomic register, Eventual leader, Fault-tolerance, Omega, Process crash, Shared memory, System model, Timer property, Timing assumptions, $t$-resilient protocol, Wait-free protocol, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1842

Dostupnosť: https://inria.hal.science/inria-00142865
https://inria.hal.science/inria-00142865/document
https://inria.hal.science/inria-00142865/file/PI-1842.pdf

The Iterated Restricted Immediate Snapshot Model

Autori: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Prispievatelia: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Zdroj: https://inria.hal.science/inria-00193683 ; [Research Report] PI 1874, 2007, pp.22.

Predmety: Algorithmic reduction, Asynchronous system, Distributed algorithm, Distributed Computability, Failure detectors, Fault-tolerance, Round-based computation, Shared memory, Topology, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: PI 1874

Dostupnosť: https://inria.hal.science/inria-00193683
https://inria.hal.science/inria-00193683v3/document
https://inria.hal.science/inria-00193683v3/file/PI-1874.pdf

A Timing Assumption and two $t$-Resilient Protocols for Implementing an Eventual Leader Service in Asynchronous Shared Memory Systems

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://inria.hal.science/inria-00142865 ; [Research Report] PI 1842, 2007, pp.19.

Predmety: Asynchronous system, Atomic register, Eventual leader, Fault-tolerance, Omega, Process crash, Shared memory, System model, Timer property, Timing assumptions, $t$-resilient protocol, Wait-free protocol, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1842

Dostupnosť: https://inria.hal.science/inria-00142865
https://inria.hal.science/inria-00142865v1/document
https://inria.hal.science/inria-00142865v1/file/PI-1842.pdf

The Iterated Restricted Immediate Snapshot Model

Autori: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Prispievatelia: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Zdroj: https://inria.hal.science/inria-00193683 ; [Research Report] PI 1874, 2007, pp.22.

Predmety: Algorithmic reduction, Asynchronous system, Distributed algorithm, Distributed Computability, Failure detectors, Fault-tolerance, Round-based computation, Shared memory, Topology, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: PI 1874

Dostupnosť: https://inria.hal.science/inria-00193683
https://inria.hal.science/inria-00193683v3/document
https://inria.hal.science/inria-00193683v3/file/PI-1874.pdf

A Timing Assumption and two $t$-Resilient Protocols for Implementing an Eventual Leader Service in Asynchronous Shared Memory Systems

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://inria.hal.science/inria-00142865 ; [Research Report] PI 1842, 2007, pp.19.

Predmety: Asynchronous system, Atomic register, Eventual leader, Fault-tolerance, Omega, Process crash, Shared memory, System model, Timer property, Timing assumptions, $t$-resilient protocol, Wait-free protocol, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1842

Dostupnosť: https://inria.hal.science/inria-00142865
https://inria.hal.science/inria-00142865/document
https://inria.hal.science/inria-00142865/file/PI-1842.pdf

The Iterated Restricted Immediate Snapshot Model

Autori: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Prispievatelia: Rajsbaum, Sergio Raynal, Michel Travers, Corentin a ďalší

Zdroj: https://inria.hal.science/inria-00193683 ; [Research Report] PI 1874, 2007, pp.22.

Predmety: Algorithmic reduction, Asynchronous system, Distributed algorithm, Distributed Computability, Failure detectors, Fault-tolerance, Round-based computation, Shared memory, Topology, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: Report N°: PI 1874

Dostupnosť: https://inria.hal.science/inria-00193683
https://inria.hal.science/inria-00193683v3/document
https://inria.hal.science/inria-00193683v3/file/PI-1874.pdf

A Timing Assumption and two $t$-Resilient Protocols for Implementing an Eventual Leader Service in Asynchronous Shared Memory Systems

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://hal.inria.fr/inria-00142865 ; [Research Report] PI 1842, 2007, pp.19.

Predmety: Asynchronous system, Atomic register, Eventual leader, Fault-tolerance, Omega, Process crash, Shared memory, System model, Timer property, Timing assumptions, $t$-resilient protocol, Wait-free protocol, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1842; inria-00142865; https://hal.inria.fr/inria-00142865; https://hal.inria.fr/inria-00142865/document; https://hal.inria.fr/inria-00142865/file/PI-1842.pdf

Dostupnosť: https://hal.inria.fr/inria-00142865
https://hal.inria.fr/inria-00142865/document
https://hal.inria.fr/inria-00142865/file/PI-1842.pdf

Electing an Eventual Leader in an Asynchronous Shared Memory System

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://inria.hal.science/inria-00109424 ; [Research Report] PI 1821, 2006, pp.19.

Predmety: Process crash, Shared memory, System model, Timer, Access cost, Asynchronous system, Bounded memory, Eventual leader, Fault-tolerance, Omega, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: C.: Computer Systems Organization/C.4: PERFORMANCE OF SYSTEMS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1821

Dostupnosť: https://inria.hal.science/inria-00109424
https://inria.hal.science/inria-00109424v1/document
https://inria.hal.science/inria-00109424v1/file/PI-1821.pdf

Minimizing Single-Usage Cache Pollution for Effective Cache Hierarchy Management

Autori: Piquet, Thomas Rochecouste, Olivier Seznec, André a ďalší

Prispievatelia: Piquet, Thomas Rochecouste, Olivier Seznec, André a ďalší

Zdroj: https://inria.hal.science/inria-00116611 ; [Research Report] PI 1826, 2006, pp.19.

Predmety: Computer Architecture, Memory Hierarchy, Cache Pollution, Single-Usage Data, Block-Usage Prediction, Hardware Prefetching, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1826

Dostupnosť: https://inria.hal.science/inria-00116611
https://inria.hal.science/inria-00116611v1/document
https://inria.hal.science/inria-00116611v1/file/PI-1826.pdf

Electing an Eventual Leader in an Asynchronous Shared Memory System

Autori: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Prispievatelia: Fernández, Antonio Jiménez, Ernesto Raynal, Michel a ďalší

Zdroj: https://inria.hal.science/inria-00109424 ; [Research Report] PI 1821, 2006, pp.19.

Predmety: Process crash, Shared memory, System model, Timer, Access cost, Asynchronous system, Bounded memory, Eventual leader, Fault-tolerance, Omega, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, ACM: C.: Computer Systems Organization/C.4: PERFORMANCE OF SYSTEMS, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1821

Dostupnosť: https://inria.hal.science/inria-00109424
https://inria.hal.science/inria-00109424/document
https://inria.hal.science/inria-00109424/file/PI-1821.pdf

Minimizing Single-Usage Cache Pollution for Effective Cache Hierarchy Management

Autori: Piquet, Thomas Rochecouste, Olivier Seznec, André a ďalší

Prispievatelia: Piquet, Thomas Rochecouste, Olivier Seznec, André a ďalší

Zdroj: https://inria.hal.science/inria-00116611 ; [Research Report] PI 1826, 2006, pp.19.

Predmety: Computer Architecture, Memory Hierarchy, Cache Pollution, Single-Usage Data, Block-Usage Prediction, Hardware Prefetching, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1826

Dostupnosť: https://inria.hal.science/inria-00116611
https://inria.hal.science/inria-00116611/document
https://inria.hal.science/inria-00116611/file/PI-1826.pdf