Výsledky vyhľadávania - "ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic"

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  1. 1

    Efficient modular operations using the adapted modular number system

    Autori: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf Véron, Pascal a ďalší

    Prispievatelia: Didier, Laurent-Stéphane Dosso, Fangan-Yssouf Véron, Pascal a ďalší

    Zdroj: ISSN: 2190-8508.

    Predmety: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]

    Dostupnosť: https://hal.science/hal-02486345
    https://hal.science/hal-02486345v1/document
    https://hal.science/hal-02486345v1/file/amns_jcen-3.pdf
    https://doi.org/10.1007/s13389-019-00221-7

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  2. 2

    RNS Modular Multiplication through Reduced Base Extensions

    Autori: Bigou, Karim Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) a ďalší

    Prispievatelia: Bigou, Karim Tisserand, Arnaud Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) a ďalší

    Zdroj: ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors ; https://inria.hal.science/hal-01010961 ; ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jun 2014, Zurich, Switzerland. pp.57-62, ⟨10.1109/ASAP.2014.6868631⟩

    Predmety: Residue Number System, Montgomery Multiplication, Finite Field Arithmetic, Asymmetric Cryptography, Elliptic Curve Cryptography (ECC), Discrete Logarithm (DL), ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: E.: Data/E.3: DATA ENCRYPTION/E.3.2: Public key cryptosystems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: Zurich, Switzerland

    Dostupnosť: https://inria.hal.science/hal-01010961
    https://inria.hal.science/hal-01010961v1/document
    https://inria.hal.science/hal-01010961v1/file/article_asap2014.pdf
    https://doi.org/10.1109/ASAP.2014.6868631

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  3. 3

    Accelerated Shift-and-Add Algorithms: Accelerated shift-and-add algorithms

    Autori: Revol, Nathalie Yakoubsohn, Jean-Claude Computer arithmetic (ARENAIRE) a ďalší

    Prispievatelia: Revol, Nathalie Yakoubsohn, Jean-Claude Computer arithmetic (ARENAIRE) a ďalší

    Zdroj: Reliable Computing. 6:193-205

    Predmety: ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.7: Ordinary Differential Equations, Computation of special functions and constants, construction of tables, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, shift-and-add algorithms, [INFO.INFO-AO] Computer Science [cs]/Computer Arithmetic, Other functions coming from differential, difference and integral equations, Numerical methods for initial value problems involving ordinary differential equations, Special ordinary differential equations (Mathieu, Hill, Bessel, etc.)

    Popis súboru: application/xml

    Prístupová URL adresa: https://link.springer.com/article/10.1023%2FA%3A1009921407000
    https://hal.inria.fr/inria-00545004
    https://dblp.uni-trier.de/db/journals/rc/rc6.html#RevolY00

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  4. 4

    Simultaneous floating-point sine and cosine for VLIW integer processors

    Autori: Jeannerod, Claude-Pierre Jourdan-Lu, Jingyan Arithmetic and Computing (ARIC) a ďalší

    Prispievatelia: Jeannerod, Claude-Pierre Jourdan-Lu, Jingyan Arithmetic and Computing (ARIC) a ďalší

    Zdroj: 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012)
    https://inria.hal.science/hal-00672327
    23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012), Jul 2012, Delft, Netherlands. pp.69-76

    Predmety: VLIW integer processor, instruction level parallelism, C software implementation, floating-point arithmetic, IEEE 754, unit in the last place, trigonometric function, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Geografické téma: Delft, Netherlands

    Dostupnosť: https://inria.hal.science/hal-00672327
    https://inria.hal.science/hal-00672327v1/document
    https://inria.hal.science/hal-00672327v1/file/Jeannerod-JourdanLu.pdf

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  5. 5

    On the Computation of Correctly-Rounded Sums

    Autori: Kornerup, Peter Lefèvre, Vincent Louvet, Nicolas a ďalší

    Prispievatelia: Kornerup, Peter Lefèvre, Vincent Louvet, Nicolas a ďalší

    Zdroj: 19th IEEE Symposium on Computer Arithmetic - Arith'19
    https://inria.hal.science/inria-00367584
    19th IEEE Symposium on Computer Arithmetic - Arith'19, Jun 2009, Portland, Oregon, United States

    Predmety: floating-point arithmetic, summation algorithms, correct rounding, 2Sum and Fast2Sum algorithms, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.0: General, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

    Geografické téma: Portland, Oregon, United States

    Dostupnosť: https://inria.hal.science/inria-00367584
    https://inria.hal.science/inria-00367584v2/document
    https://inria.hal.science/inria-00367584v2/file/arith19.pdf

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  6. 6

    FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

    Autori: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a ďalší

    Prispievatelia: Alias, Christophe Pasca, Bogdan Plesco, Alexandru a ďalší

    Zdroj: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

    Predmety: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Dostupnosť: https://inria.hal.science/inria-00606977
    https://inria.hal.science/inria-00606977v1/document
    https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

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  7. 7

    Multi-operand Decimal Adder Trees for FPGAs

    Autori: Vazquez, Alvaro de Dinechin, Florent Computer arithmetic (ARENAIRE) a ďalší

    Prispievatelia: Vazquez, Alvaro de Dinechin, Florent Computer arithmetic (ARENAIRE) a ďalší

    Zdroj: https://inria.hal.science/inria-00526327 ; [Research Report] RR-7420, INRIA. 2010, pp.20.

    Predmety: Decimal arithmetic, IEEE 754-2008, BCD multi-operand addition, carry-ripple adder, pipelined adder trees, FPGA implementation, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.0: General, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

    Dostupnosť: https://inria.hal.science/inria-00526327
    https://inria.hal.science/inria-00526327v1/document
    https://inria.hal.science/inria-00526327v1/file/RR-7420.pdf

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  8. 8

    Code generation for argument filtering and argument reduction in elementary functions

    Autori: de Dinechin, Florent Jeannerod, Claude-Pierre Pfannholzer, David a ďalší

    Prispievatelia: de Dinechin, Florent Jeannerod, Claude-Pierre Pfannholzer, David a ďalší

    Zdroj: SCAN 2010: 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics ; https://inria.hal.science/inria-00544808 ; SCAN 2010: 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics, Revol, Nathalie and de Dinechin, Florent and Jeannerod, Claude-Pierre and Lefèvre, Vincent and Louvet, Nicolas and Morin, Sèverine and Nguyen, Hong Diep, Sep 2010, Lyon, France

    Predmety: scientific computing, computer arithmetic, validated numerics, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.4: MATHEMATICAL SOFTWARE, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

    Geografické téma: Lyon, France

    Dostupnosť: https://inria.hal.science/inria-00544808

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  9. 9

    An efficient rounding boundary test for pow(x,y) in double precision

    Autori: Lauter, Christoph Quirin Lefèvre, Vincent Computer arithmetic (ARENAIRE) a ďalší

    Prispievatelia: Lauter, Christoph Quirin Lefèvre, Vincent Computer arithmetic (ARENAIRE) a ďalší

    Zdroj: ISSN: 0018-9340 ; IEEE Transactions on Computers ; https://inria.hal.science/inria-00583988 ; IEEE Transactions on Computers, 2009, 58 (2), pp.197-207. ⟨10.1109/TC.2008.202⟩.

    Predmety: floating-point arithmetic, correct rounding, power function, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: G.: Mathematics of Computing/G.1: NUMERICAL ANALYSIS/G.1.0: General/G.1.0.0: Computer arithmetic, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic

    Dostupnosť: https://inria.hal.science/inria-00583988
    https://doi.org/10.1109/TC.2008.202

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